What is Going on with Sub-20nm Flash?
This week I’ll be participating in a panel discussion at the Flash Memory Summit in Santa Clara, CA. The panel’s topic, Flash Below 20nm: What is Coming and When?, couldn’t be more timely. Particularly in light of a leading NAND manufacturer’s recent announcement that they will begin mass production of the semiconductor industry’s first 3D vertical NAND flash memory later this year.
3D NAND presents some significant changes to the traditional semiconductor manufacturing model. For example, the physical characteristics of 3D NAND (i.e. NAND cells are built on the Z axis, not just X and Y) are such that the challenges typically involved in the lithography portion of the process are greatly reduced. This means design rules for less advanced process nodes (say 50nm or less) can be used in sub 19nm 2D NAND equivalent technology nodes, which shifts process step intensity from costly lithography equipment to deposition, etch, and process control technologies. But this benefit comes with new challenges. For instance, building on the Z plane places greater emphasis for accuracy on the deposition and etch processes.
As the image below shows, building layers of NAND cells in the Z axis means multiple deposition layers and higher aspect ratios, which increases the importance of controlling layer uniformity and etching precision. With over 50 layers needing to be spread precisely over an entire 300mm wafer, precision deposition with tight process control along with high productivity, become very important. Gate and isolation critical dimensions (CDs) are controlled by lithography + SADP (self-aligned double patterning) in the case of 2D NAND, while deposited film thickness determines these CDs for 3D NAND.
3D NAND is changing semiconductor manufacturing at both the business and engineering levels. To learn more about these changes, I invite you to listen in on the panel discussion this week.