Supply Chain Collaboration for 3D Interconnect Applications

3D Interconnect applications are attracting more and more interest from a large number of players in the semiconductor industry. I recently participated in two conferences (IWLPC – International Wafer Level Packaging Conference and IMAPS- International Microelectronics and Packaging Society Conference) on this topic to keep up-to-date on the new activities and developments in the industry and to share our latest advancements achieved with EMC3D consortium.

EMC3D consortium is an international consortium of leading equipment (Applied Materials, EVG, Datacon, WSR), materials (AZ-EM, Dow Chemicals, Enthone, Brewer Science) and technology members (IZM Fraunhofer, LETI, KAIST, Samsung Institute of Technology, Texas A&M), founded in 2006 with the objective of developing robust and manufacturable processes for supporting chip stacking using through-silicon via (TSV) technology.

In the beginning, the main focus of the consortium was to develop robust and cost effective unit processes, and in the past couple of years a significant amount of work was performed to seamlessly integrate all the unit processes required for vertical stacking using TSV technology. Through strong collaboration it was possible to identify early in the developmental stage several of the challenges associated with this technology and develop solutions to address them while at the same time reducing the cost, enabling thus faster transition of this technology from development to production.

The conferences I recently participated in, similar to others in the past couple of years, had a high number of presentations on 3D Interconnect using TSV technology, highlighting the advancements achieved so far as well as what needs to be addressed in order to fully adopt this technology into production. Several questions addressing areas of concerns as well as future trends were raised during the 3D panel discussion from the IMAPS 2010 conference. Professor James Lu from RPI, a strong supporter of TSV technology, moderated a panel of well-known experts in the industry working on this technology. Panelists included: Phil Garrou, Consultant, Microelectronics Consultants of NC; Klaus Hummler, Senior Principal Engineer, Sematech; Urmy Ray, Senior Staff Engineer, Qualcomm; Nicolas Sillon, Group Manager Packaging and Integration, CEA-Leti Minatec; Dorota Temple, Senior Fellow and Program Director, RTI International and myself as the Program Director EMC3D Consortium.

Photo credit: Phil Garrou

The discussion revolved around several key aspects with respect to 3D-TSV stacking evolution including, technical areas that have seen major progress in the past year, key barriers that still exist for TSV adoption, roadmaps, commercial readiness, the role of supply chain in adoption of this technology as well as production timelines for various devices and applications, and last, but not least key business roadblocks for TSV manufacturing hand-off.

Early industry estimations of production starts were delayed because design and test solutions are not yet fully developed although some standardizations in design have been reported. As an intermediary step, Interposer (gathering high interest in the industry these days) is currently used until 3D ICs are fully supported by all supply chain members involved. Additionally, Via processing is well developed and integrated solutions are available.

We don't have to go very far to see a great example - the TSV line at Applied's Maydan Technology Center (located in Sunnyvale, CA) and the integration team the company has to support its customers and the industry is a great group of experienced, passionate and hardworking engineers - which I am proud to be a part of.

As Phil Garrou, a well-known and recognized expert in 3D applications and whom I’ve had the pleasure to work with, commented during a recent panel discussion, “the roadmaps of the major players in the industry appear to be in sync, estimating commercialization in the 2011-2012 timeframe.”

We are already seeing CMOS image sensors in production. Xilinx recently announced the use of TSV for FPGA devices and the industry will next experience adoption of TSVs for DRAM, followed by memory/logic integration. According to Ray Urmi, Qualcomm is foreseeing 2012 as the year of commercially available 3D-TSV products; Nokia is also working on 3D technologies, with product introduction  estimated for 2013.

All three chip stacking methods, chip-to-chip (C2C), chip-to-wafer (C2W) and wafer-to-wafer (W2W), will continue to be considered. For memory stacking, since the sizes of the dies are similar and due to cost pressure, W2W will most likely be the stacking approach applied. When it comes to heterogeneous integration, the other two methods (C2C, C2W) are strongly considered, due to known-good-die (KGD) issues and variations in the size of dies that will make W2W less suitable.

The importance of supply chain collaboration has been raised as being very critical to the development and successful implementation of any new technology. Also, converging towards a common roadmap will only help those involved with this technology and the industry to faster perfect this technology and robustness of its applications and be ready for high volume manufacturing production.

Stay tuned for more blog posts on 3D technologies. Send me any questions or suggestions for future posts on 3D Integration.

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