Semiconductors

Getting from R&D to high-volume manufacturing of new technology nodes is a complex process gated primarily by the ability to detect and correct defects. The methods used by the industry to perform defect inspection and review have remained relatively the same for decades. It is now time for a new approach—one that is optimized for the AI Era.

2020 will be remembered most for the challenges of COVID-19. In the world of technology, it will be remembered for accelerating digital transformations that would have taken many more years to play out. Entering 2021, the dependency between the global economy and semiconductors is greater than it’s ever been. At the same time, the way chips are being made is changing as traditional Moore’s Law scaling slows. Applied Materials is dedicated to driving new ways to help our customers continue to deliver improvements in chip power, performance and cost, in record time.

Selective processing is increasingly being used to create, shape and modify materials and features in semiconductor manufacturing. In this blog I explain what selective processing is and why it’s critically important to the future of chip scaling.

Recently I participated in a fascinating panel discussion with experts from Arm, Google, Intel, Microsoft, UC Santa Barbara and VMware to explore how Big Data, AI and cloud computing can be used to help mitigate—rather than contribute to—climate change.

Watch the video replay of Applied Materials CEO Gary Dickerson’s keynote at SEMICON West to hear about new initiatives Applied is driving to enable a more sustainable company, industry and world.

Applied’s newest Integrated Materials Solution solves the challenge of selective tungsten deposition, enabling simultaneous improvements in chip power, performance and area/cost (PPAC) in the most advanced foundry-logic nodes.

With EUV-enabled advances in 2D scaling pushing the limits of conventional materials engineering techniques, a breakthrough is needed to overcome increases in contact resistance and enable continued improvements in chip performance, power and area/cost (PPAC).

The advent of EUV lithography is helping overcome transistor scaling challenges, but new innovations in materials engineering are needed to enable performance and power to scale as well.

My latest blog describes three innovative patterning techniques that complement EUV and accelerate the industry’s roadmap for logic and DRAM scaling.