Semiconductors

The advent of EUV lithography is helping overcome transistor scaling challenges, but new innovations in materials engineering are needed to enable performance and power to scale as well.

My latest blog describes three innovative patterning techniques that complement EUV and accelerate the industry’s roadmap for logic and DRAM scaling.

Amid a slowdown in classic Moore’s Law scaling, heterogeneous design and advanced packaging play a growing role in the logic roadmap.

Applied is honored to be recognized among Intel’s 2019 Preferred Quality Supplier (PQS) award winners.

Our latest in a series of blogs inspired by Applied Materials’ panel discussion at IEDM explores where and how data should be processed and stored to drive computing efficiency while curbing energy consumption.

Applied Materials moderated a thought-provoking panel discussion during IEDM which showed that while there is no single path to achieving continued improvements in chip performance, power and area-cost, the industry will be well-served to search for solutions together.

What’s clear from the panel discussion I recently moderated with Facebook, IBM, Intel, Stanford and TSMC is that the semiconductor design and manufacturing model is evolving and will look extremely different in the years ahead.

Join us on Dec. 10 in San Francisco as we discuss new ways of improving chip performance, power and area-cost beyond traditional Moore’s Law scaling.

Where can the industry test codesigned chip innovations for the AI Era—to accelerate the future of computing, from materials to systems? The answer is: our new Materials Engineering Technology Accelerator (META Center), which—I’m delighted to announce—is now open for collaboration.