Applied’s newest Integrated Materials Solution solves the challenge of selective tungsten deposition, enabling simultaneous improvements in chip power, performance and area/cost (PPAC) in the most advanced foundry-logic nodes.
With EUV-enabled advances in 2D scaling pushing the limits of conventional materials engineering techniques, a breakthrough is needed to overcome increases in contact resistance and enable continued improvements in chip performance, power and area/cost (PPAC).
The advent of EUV lithography is helping overcome transistor scaling challenges, but new innovations in materials engineering are needed to enable performance and power to scale as well.
Our latest in a series of blogs inspired by Applied Materials’ panel discussion at IEDM explores where and how data should be processed and stored to drive computing efficiency while curbing energy consumption.
Applied Materials moderated a thought-provoking panel discussion during IEDM which showed that while there is no single path to achieving continued improvements in chip performance, power and area-cost, the industry will be well-served to search for solutions together.
What’s clear from the panel discussion I recently moderated with Facebook, IBM, Intel, Stanford and TSMC is that the semiconductor design and manufacturing model is evolving and will look extremely different in the years ahead.
