Not All Semiconductor Innovation Occurs at the Leading Edge

On Sept. 8, Applied Materials will host its third Master Class event of the year, which will focus on two key growth areas for the company: ICAPS along with heterogeneous design and advanced packaging. In this blog I will preview the ICAPS portion by explaining why Applied formed this business group, and I’ll give two examples where innovation is needed to drive improvements in the power, performance, area, cost and time to market (PPACt) of ICAPS devices.

In 2019, Applied formed ICAPS, a horizontal business unit that harnesses all of Applied’s technologies to bring focus to specific vertical markets that have unique technology requirements. ICAPS stands for IoT, Communications, Automotive, Power and Sensors. As the products we use and the world around us get smarter each year, they demand more silicon content, most of which is not leading-edge logic and memory. We are seeing rapid growth in IoT devices for the farm, factory, office and home. And they are filled with embedded logic and lots of ICAPS content such as RF communications silicon, power devices, CMOS image sensors, MEMS devices and analog to digital converters. Many of these devices are still built on 150mm and 200mm wafers, and planar logic devices such as 28nm SoCs are more than capable for a wide range of embedded computing workloads. The industry still talks about “trailing nodes” and “legacy nodes,” but those terms miss the renaissance of innovation that’s happening in the ICAPS markets.

As the world becomes more digital, ICAPS devices take on an increasingly valuable role. If advanced logic and memory are like the brains of a computing system, then ICAPS devices are like the eyes, ears, noses and skin—each essential to life in a digital world.

Most importantly, the ICAPS markets need materials engineering so that we can have better and more capable digital devices each year. Let’s explore two use cases influencing the future of smartphone and automotive design.

CMOS Image Sensors Need Materials Engineering to Continue Scaling

CMOS image sensor (CIS) arrays enable the multiple cameras in today’s smartphones and smart cars. Manufactured at nodes between 45nm and 90nm, they’re arranged into millions of individual light sensitive pixels in groups of three—one each for blue, green and red. Today, each pixel is just under 1um wide and in the range of 6-10um deep, and each is isolated from its neighboring pixel (see Figure 1).

Figure 1: In a CIS array, each pixel collects light rays that pass through color filters. If the light ray strikes an electron currently bound to one of the silicon atoms in the pixel, then that electron is freed and makes its way to the bottom of the pixel where it is registered as a light signal.

The conventional means for achieving higher CMOS image sensor resolution is to use a planar scaling process that reduces feature sizes and allows more pixels to be squeezed into a given area. A major obstacle to this manufacturing approach is maintaining sufficiently high levels of dynamic range. This refers to the ability to capture very low light and bright light at the same time, which becomes more difficult because smaller pixels are prone to saturation that can introduce image artifacts.

To enable continued 2D pixel scaling through the next several process nodes, smartphone camera designers will require innovations in materials engineering that enable new isolation and passivation techniques. For example, as more pixels share the same die area they are increasingly subject to crosstalk that can lead to pixel noise and poor image quality. Deep isolation trenches between pixels are required to separate individual signals; however, as planar pixel scaling progresses, these isolation trenches become taller and thinner, creating extremely high aspect ratios. Today these ratios are in the range of 40:1 but could soon reach 60:1 and even 100:1.

In the upcoming ICAPS Master Class, Applied will describe innovative solutions to increase isolation trench aspect ratios, improve signal-to-noise ratio and enable continued pixel scaling.

Silicon Carbide: Innovation Needed to Enable Transition to Larger Wafers

As my colleague Llew Vaughan-Edmunds recently wrote, the electrification of vehicles is disrupting the global transportation industry. It’s also dramatically altering the quantity and variety of chips used in cars. Today’s electric vehicles (EVs) already require nearly twice the semiconductor content by dollar value as compared to internal combustion engine vehicles. By 2030, we could see another doubling based on the need for chips used to support varying levels of Advanced Driver Assistance Systems (ADAS).

On the device side, silicon carbide (SiC) MOSFETs are expected to play an increasingly prominent role in everything from EV power distributors and regulators to the high-voltage traction inverter modules that power EV motors. Thanks to their fast switching speed—and high voltage and current handling capability—SiC MOSFETS enable smaller and lighter motor drive systems to be used, and this helps further increase EV range.

To meet the burgeoning demand for SiC power devices, chipmakers would like to accelerate the transition from 150mm wafers to 200mm, nearly doubling die output per wafer. Two materials engineering challenges are SiC wafer surface quality and electron mobility. Compared to silicon, SiC is inherently tougher, and natural defects can cause disruptions in the lattice structure of the device material which degrades electrical performance, power efficiency, reliability and yield. SiC wafers act as a base upon which additional SiC layers will be grown using epitaxy. Surface quality is critically important because any defects on the surface of the wafer will propagate through the upper layers, affecting the devices (see Figure 2). Creating a near-perfect surface on such a hard material is a key challenge, but Applied is developing advanced materials engineering solutions to optimize raw SiC wafers for production.

Figure 2: In SiC devices, electron mobility is degraded by crystal defects originating from the substrate.

In addition, turning the SiC material into functioning power devices also requires injecting ions that enable current to flow as designers intend. Here too, the hardness of SiC material and the need for lattice integrity pose challenges to the approaches used in silicon wafers: ion implantation and diffusion. New solutions will be detailed at the Master Class.

As these two use cases illustrate, the ICAPS markets are all about new innovations in materials engineering. With decades of experience at all nodes and wafer sizes, Applied is in a unique position to help ICAPS customers accelerate innovation in their markets. Applied plans to enable its customers by combining unit process leadership with co-optimized and integrated solutions.

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