It’s Time for a New Playbook for Finding and Correcting Defects in Advanced Chips
Semiconductors are the foundation of all technology inflections. The PC Era was ushered in by powerful microprocessors. The Mobile Era by advances that put high-performance, low-power chips in smartphones. The Cloud Era with processors and banks of memory and storage in huge data centers. While these markets remain large and growing, we are now entering the AI Era fueled by the Internet of Things (IoT), Big Data and 5G, shaped by new types of computing architectures and chip designs. Semiconductor progress has never been more critical to the growth of the global economy.
The stakes are high if we cannot continue to advance the semiconductor technology roadmap with high-performance logic and memory devices in the enormous volumes required for this new era. Getting from R&D to high-volume manufacturing of new technology nodes is a complex process gated primarily by the ability to detect and correct defects. The methods used by the industry to perform defect inspection and review have remained relatively the same for decades. Is it time to rethink our approaches?
This is the first blog in a series examining challenges around defect detection and correction. Any obstacles to advancement in the semiconductor industry ripple forward into the much larger global electronics ecosystem. The faster those obstacles can be overcome, the faster the world moves forward. Time is a critical factor.
Time is Money
Given the extraordinary cost of being in the semiconductor industry, its business imperatives revolve around time: time to development, time to volume production, time to market, and time to revenue. And the most critical parameter is time to yield. Even a small acceleration in the time it takes to get from R&D of new processes to the early ramp phase and then to high-volume manufacturing equates to billions of dollars in value for chipmakers (see Figure 1).
The opposite is also true, of course. Delays in yield improvement cost time, money and market share in the new computing era which fuels the most valuable businesses the world has ever seen.
Defect detection is the gating factor in yield improvement. The faster yield-killing defects can be found, the faster they can be corrected. However, defects are getting harder to find. For example, ever-smaller line widths turn tiny nuisance particles into yield-killers. When building sophisticated 3D transistors, and when executing complex multi-patterning steps, small variances can multiply to produce yield-killing defects. This further complicates matters because a defect can be revealed long after its root cause occurred: every subsequent process step following the introduction of the defect is time and money wasted.
As the complexity of chips is rising and defects are becoming increasingly difficult to find, the industry should be inspecting more. But in reality, the exact opposite is happening—inspection steps are being limited. Why is that?
The fab economic model becomes a major challenge at this juncture. For every nanometer of advancement, the number of wafer processing steps grows rapidly. More steps to inspect equals more inspection cost. Additionally, the increasing sophistication of the optical scanners used to find defects has increased their cost as well. More cost per scanner equals more cost per wafer scan (see Figure 2).
As a result, engineers are inspecting at fewer steps than they would like simply to keep their process control budgets from skyrocketing. Of course, limiting the number of inspection steps results in less of the data needed to accelerate defect detection, traceback, root cause analysis and correction—and thereby accelerate time to yield. Yet, these inspection costs are very real and cannot be wished away. The number of inspection steps inserted into the process recipe is one of the few points of cost control available. Fabs budget a certain amount of inspection dollars, engineers gather as much data as they can afford, and everyone hopes for the best.
The inspection paradigm used today was developed in a very different time. Not only was Moore’s Law operating on schedule, defects that were mere nuisance blips on a wafer map in previous generations are now yield killers. The reality is that the industry is inspecting less and therefore collecting less data—relative to the soaring complexity of the challenge—precisely when we should be inspecting more. What we need is a new playbook for process control that can accelerate time to yield without breaking the fab economic model. This is an innovation imperative for the semiconductor industry.
In my next blog, I’ll describe the breakthroughs needed to revolutionize defect detection and correction in the AI Era.