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Dr. Sony Varghese is director of strategic marketing for memory in the Semiconductor Products Group at Applied Materials. In this role, he is involved in identifying challenges to future key inflections in the memory industry. Prior to Applied Materials, he worked on developing various memory technologies within the R&D organization at Micron Technologies. Dr. Varghese has over 20 U.S. patents issued or pending in the area of semiconductor processing and integration. He holds a master’s degree in materials engineering from The National Institute of Technology Surathkal in India and a Ph.D. in mechanical and materials engineering from Oklahoma State University.
To help the industry meet global demand for more affordable, high-performance memory, Applied Materials today introduced solutions that support three levers of DRAM scaling: a new hard mask material for capacitor scaling, a low-k dielectric material for the interconnect wiring, and the adoption of high-k metal gate transistors for advanced DRAM designs.
The AI Era of computing is fueling exponential growth in data generation, and the entire technology ecosystem depends on the semiconductor industry finding new ways to scale DRAM architectures to keep pace with bit demand. New hard mask patterning films can enable thinner capacitors with the highest possible aspect ratios, while new dielectric insulating materials can reduce the spacing between metal lines, both resulting in new ways to shrink.