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Kevin Moraes is vice president of Products and Marketing in the Semiconductor Products Group at Applied Materials. He leads teams that develop product strategies and investment priorities, manage product lines, and communicate strategies to stakeholders. Dr. Moraes received his Ph.D. in materials science and engineering from Rensselaer Polytechnic Institute, and a bachelor’s degree in chemical engineering from Annamalai University. He also holds an MBA from the Hass School of Business at the University of California, Berkeley.
As classic 2D scaling with EUV shrinks on-chip wiring, electrical resistance increases exponentially, creating power, performance and heat challenges. Moreover, as transistor counts continue to increase exponentially while 2D scaling slows, die sizes are increasing to the point where designers are hitting the “reticle limit” of chip designs. Fortunately, innovations in chip wiring will enable chipmakers to continue delivering improvements in performance and power—while advances in chip integration will give designers virtually unlimited transistor budgets. In short, “new ways to wire and integrate chips” will enable amazing computing experiences for everyone.
Applied Materials moderated a thought-provoking panel discussion during IEDM which showed that while there is no single path to achieving continued improvements in chip performance, power and area-cost, the industry will be well-served to search for solutions together.