First Metallization Solution for High-Volume Manufacturing of TSVs
Through-silicon via (TSV) technology is being implemented as an advanced packaging alternative to meet intensifying consumer demand for more functionality at lower power and greater speed in smaller, mobile products. TSVs help satisfy these demands by offering chipmakers improved power and form factor efficiencies through vertical chip stacking compared to wire bonding and flip chip stacking. TSVs are short, vertical electrical connections that pass through a silicon wafer, enabling electrical connections from the active side to the backside of the die. TSV provides the shortest interconnect path, and is one of the best candidates for 3D/vertical integration. The well-known hybrid memory cube (HMC) that stacks DRAMs on top of a logic layer is a great example. Each layer of the chip is connected using TSVs. A single HMC can deliver more than 15x the performance while consuming 70 percent less energy per bit than DDR3 DRAM technologies.
The recently announced Endura® Ventura™ PVD is the first system designed specifically for TSV metallization in high-volume manufacturing and leverages more than 20 years of Endura PVD leadership. Besides being able to process the industry-proven tantalum barrier, the Ventura system offers a first-time industry capability to deposit titanium as an alternative production-worthy, lower cost barrier – an excellent example of Applied’s precision materials engineering expertise.
Why is dedicated PVD technology for TSVs needed?
TSVs are at least 1000 times deeper than typical copper interconnect structures, which presents a major challenge for current PVD technology. PVD is a line-of-sight process; as such, it is challenged to deposit materials deep within such structures. Consequently, much thicker layers are required to produce a reliable copper diffusion barrier and continuous seed layer inside the via for robust gap fill. This low-productivity method is also costly and unreliable – thus the need for PVD technology dedicated for TSV metallization.
With the Ventura system we’ve improved the line-of-sight performance through magnetron source design and improved directionality of the metal ions. These enhancements enable sputtered materials to reach deep into the vias, resulting in improved coverage. Bottom coverage of the Ventura tantalum barrier, for example, improves by 50 to 300 percent, enabling superior gap fill with reliable TSVs.
The barrier-seed film stack created by the Ventura PVD system is up to 50 percent thinner than that previously required to achieve void-free gap fill. On the graph below, the X-axis shows tantalum barrier thickness; the Y-axis shows copper seed thickness. We usually define a window as the combination of barrier and seed thicknesses that will enable void-free gap fill. The copper interconnect PVD, the orange line, defines the window in which the minimum barrier and seed thicknesses are required to achieve that gap fill performance. With Ventura PVD, that window is shifted downwards towards the left, meaning a much thinner barrier and seed combination is now needed to achieve that same gap fill. This is a result of improved coverage deep inside the TSV where a PVD line-of-sight deposition technique is limited.
Ventura lowers the cost of ownership while delivering superior metallization results. Even with a tantalum and copper combination, Ventura reduces the costs of production up to 50 percent, because a much thinner film is required to achieve good gap fill; this means less material costs per wafer and shorter processing time, which increases productivity. With the more cost-effective titanium, costs are expected to be reduced up to 20 percent.
Integrated with the copper seed process on the Endura platform, high-quality films promote the excellent gap fill essential to reliable device performance. Additional benefits include copper interconnect knowhow and the same dependable Endura platform relied on for 24 years.