Examining Emerging Memory Technologies and 3D Architectures at IITC

Emerging memory technologies and the shift to 3D architectures have the potential to overcome current memory limitations in speed, power consumption, reliability and cost to support future data-centric computing trends. And, as evidenced by the considerable investments being made in the various new memories — PCRAM, STTRAM, OxRAM and CBRAM, and 3D architectures such as 3D XPoint™ memory and 3D ReRAM, there is broad interest and competition to develop these technologies for future applications and in particular, for the commercial Internet of Things (IoT) market.

I’ll be giving an invited talk at the International Interconnect Technology Conference  (IITC) in San Jose this week to review the status of these new memories and highlight the integration and high volume manufacturing challenges. Below is a brief outline of some of the interconnect issues and the need for new materials.

The first thing to know about emerging non-volatile memories (NVM) is they operate very differently from the widely used and highly commercialized DRAM, SRAM and flash memories (NAND and NOR). Emerging memories are based on physics mechanisms rather than charge-based mechanisms. For example, instead of manipulating electrons, PCRAM uses material phase change generated by electrically induced heat that yields different resistances. STT-MRAM uses spin-polarized current to change the magnetization of magnetic materials so that the resistance of two magnetic layers changes to high and low when the magnetization between them is parallel or anti-parallel, resulting in a phenomenon known as the giant magnetoresistive effect. And, OxRAM and CBRAM use local oxygen vacancy or metal ions that drift in and out of a narrow path pre-constructed by the electrical field and current.

As non-volatile storage technologies using no-charge based mechanisms, the new memories exhibit much faster operation speeds and greater erase/write cycle endurance than NAND flash (NVM). Another advantage is they can be readily integrated using standard CMOS Cu BEOL technology, making them very appealing for high-volume manufacturing.

One of the most important parameters of NVM is data retention. This attribute is critical for automotive control and future IoT applications, as these involve extreme operational conditions, such as high temperatures, current flash memory is unsuitable. To achieve high-temperature data retention and prevent data loss, it has been found that high program energy is required (typically current density in the range of 3-10MA/cm2). The problem with this current density is it’s extremely challenging for commonly used metal wires and contacts (Cu and W) as it approaches the electro-induced migration threshold.

Another issue is the need for high-density memory to scale to the 20nm dimension to be competitive. At this scale, the metal requirements become more stringent as scattering impacts the efficient flow of electrons. This condition worsens as the small wires scale further. Innovations new conducting materials are needed that mitigate scattering loss as features scale to sub-20nm is needed, as well as solutions that reduce material loss during integration from such effects as oxidation and plasma damage.

Typically, the new NVMs operate between the nanosecond (STTRAM, OxRAM) and microsecond (CBRAM, PCRAM). For these memories, parasitic capacitance is a larger issue to RC delay than for flash NVM. To ensure high-speed operation, implementing a range of new materials is expected, including magnetic and phase change materials — both of which are very different from traditional Si IC materials and low k materials. Integrating the new materials will require some process changes. Additional parasitic impact can still emerge as may be the case with the OxRAM filament as its size is determined by the amount of atom drift and can be disturbed by a discharge of parasitic capacitance.

Cost is a historical factor driving memory roadmaps. And the costs associated with patterning, as well as reaching limitations in operational basics and in the number of electrons, have made continued 2D scaling untenable. Scaling vertically into the third dimension, for example with 3D NAND and 3D XPoint memory, reduces patterning requirements and allows the industry to continue on its traditional cost reduction curve.

However, the high aspect ratio structures of 3D designs produce new deposition and etch challenges. To achieve further overall cost reductions, metal wires are being shared by multiple memory cells, but this adds to the integration challenge as the typical damascene process is not easy to implement in 3D architectures. Metal material sensitivity to etching and dielectric encapsulation is increasing dramatically, creating the need for material changes. This is especially important for the 3D XPoint technology where an x-y grid process defines an individual device comprising a selector, memory and metal wire as either bit line or word line.

I hope this preview of my talk is interesting and informative.

3D XPoint is a trademark of Intel Corporation or its subsidiaries in the U.S. and/or other countries.

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