Building Blocks to Boost Solar Productivity (Part 1)

As the need for clean energy increases, engineers are working to expand production and improve the efficiency of crystalline silicon (c-Si) solar factories. Five years ago, a 30 MW solar fab was a competitive size. Now, companies routinely plan 300 MW-scale fabs, and some are considering fabs on the scale of 3 GW over the next few years. A key driver in this increase in fab scale is the goal of producing solar modules at a cost of less than US$1 per watt.

This week we are featuring a three part series that looks at the interrelated building blocks that are key contributors to meeting this goal for c-Si PV:

  • Higher Efficiency Cells
  • Thinner Wafers and Higher Throughputs
  • Advances in Automation

Higher Efficiency Cells

One approach to increasing cell efficiency is “selective emitter” technology in which the conductance of the emitter– i.e. the n-type phosphorous-containing region on the cell front surface – is decreased over much of the cell area so as to increase photocurrent generation and is selectively increased under the front metal grid contacts so that the front metal grid makes a lower-loss contact to the underlying silicon (Figure 1). A traditional uniform emitter is a compromise between making low-loss contacts by reducing emitter sheet resistance and transmitting more photons by increasing the emitter sheet resistance. By selectively decreasing emitter sheet resistance only under the front metal contacts and increasing emitter sheet resistance elsewhere, one can simultaneously minimize contact-related resistive losses and maximize photocurrent generation.

The precise local emitter doping required for an efficient selective emitter can be formed by various methods, including deposited dopants, deposited etchants, patterned wet etch masks, spatially-defined ion implantation, etc. Given that most cell manufacturers already use industrial screen printing for applying front metal grids it is convenient and cost effective for them to use closely related screen printing techniques to form the selective emitter. The key to using low-cost screen printing for selective emitter processing is to use a high-precision printer that allows one to align the front metal grid to precisely overlay the highly-doped selective emitter regions. For example, Applied Materials’ Baccini Coating Systems division offers high-volume screen printers with an Esatto upgrade that provides the required precision and repeatability. The cell efficiency gain achieved with selective emitter technology varies depending on the specifics of the cell, e.g. wafer quality, baseline diffusion process, baseline grid process, etc.; but an efficiency gain of 0.5 % absolute is possible.

Figure 1 The selective emitter is a heavily-doped region placed directly under the metal line.

A key factor in optimizing the selective emitter efficiency gain is a re-tuning of the metal grid pattern so that the photocurrent and photovoltage gains are not negated by lateral “spreading resistance” losses in the now-more-resistive emitter between the grid fingers. The re-tuning of the metal grid pattern generally entails decreasing the spacing between grid fingers, hence increasing the total number of grid fingers, which in turn increases the total grid coverage and decreases the cell photocurrent.  The optimized balance between gains and losses is easier when using a fine-line metallization technology to make the grid.

Fine line metallization – defined broadly as methods capable of forming a continuous high-conductance grid with finger widths below 100 microns – provides stand-alone advantages including lower optical losses due to metal coverage and lower grid metals costs use due to lower paste consumption, but fine line metallization is of particular leverage when combined with selective emitter technology.  There are a variety of fine line metallization technologies, including advanced screen printing, ink jet printing, aerosol printing, electroless and electroplating, etc.  As with selective emitter, given that most c-Si cell manufacturers already use industrial screen printing for high-through-put metallization it is convenient and cost effective for them to use advanced screen printing techniques such as “double printing” to achieve the desired fine line metallization.

“Double printing” is simply printing a metal grid pattern, then over-printing another layer of metal exactly on top of the first to achieve a tall, narrow grid so that grid fingers shadow less (due to their being more narrow) while still conducting well (due to their being taller).  Standard one-layer printing requires a relatively wide grid to achieve adequate conductance at typical layer thicknesses.  Double printing increases the total layer thickness so that one can achieve equal conductance with narrower grids (figure 2).  Narrow, tall, double-printed grids cover less of the cell’s front surface so the cell has a higher photocurrent.  Double-printing can be used alone to directly substitute for traditional single printing to provide an efficiency gain of up to 0.25 % absolute, or can be combined with selective emitter technology for overall gains of 0.7 % absolute or higher.

Figure 2 Decreasing linewidth reduces shadowing of the active area, increasing potential efficiency.

In all cases – selective emitter, fine-line metallization such as double printing, or combinations of selective emitter and fine-line metallization – an initial material is precisely overcoated with another material to achieve superior results. This precision overcoating requires a combination of good-quality initial coating, high-sensitivity detection of the initial material (e.g. the high-conductance selective emitter regions), precise alignment of the second patterned coating to the first, and consistent coating placement; and these requirements must be met on large thin high-value cells. PV equipment providers are developing a wide array of approaches to these challenges.  

Further improvements in cell efficiency are being pursued through the use of innovative cell structures that place all the contacts on the back surface of the wafer, eliminating the shadowing effect entirely.  Candidate structures include metal wrap through, emitter wrap through and various integrated back contact structures. These structures impose various new requirements on PV tool builders and materials suppliers, e.g. high-speed hole drilling in fragile Si wafers, interdigitated n- and p-type contacts, low-loss interconnection of high-current all-back-contact cells, etc. The challenge is to deliver efficiency gains while maintaining low cell processing and module assembly costs, and to deliver these gains at ever increasing scale on thinner wafers.

Check back tomorrow for part two, “Thinner Wafers and Higher Throughputs,” of this three part series.

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