Ofer Adan

At the recent SPIE Advanced Lithography conference, my keynote presentation focused on how improvements in metrology, multi-patterning techniques and materials can enable 3D memory and the critical dimension (CD) scaling of device designs to sub-10nm nodes.

Applied Materials recently hosted a panel discussion with several distinguished semiconductor industry speakers as part of the SPIE Advanced Lithography conference earlier this month, which I had the honor of moderating. The panel discussion, a retrospective look at the 25 years of technology developments in metrology, inspection and process control was co-hosted by Chris Raymond, technology director at Nanometrics, Inc. and Chair of the SPIE Conference.

Applied Materials is sponsoring an interactive panel discussion celebrating 25 years of industry innovation in metrology, inspection, and process control at this year’s SPIE Advanced Lithography conference in San Jose, California.The event — a retrospective look at 25 years of technology developments — will gather speakers from top semiconductor manufacturers and lithography related industry, including ASML, Samsung and Mentor Graphics, in an informal exchange of opinions on what they view as key milestones in the evolution of lithography and what they foresee as major technology trends over the next few years.