PPACt

The Fourth Era of Computing Needs More than Advanced Logic and Memory Chips

At the Applied Materials Master Class today, we highlight two fast-growing and highly enabling areas of the semiconductor industry. “ICAPS” silicon powers billions of new devices on the edge—including electric vehicles. No longer an afterthought, packaging now enables the benefits associated with Moore’s Law to continue even as 2D scaling slows. Today’s class demonstrates that the AI Era requires innovation across a wide range of technologies, from the edge to the cloud.

Heterogeneous Design and Advanced Packaging Enable Advances in PPACt™ Even as Classic Moore’s Law Scaling Slows

Applied’s upcoming, Sept. 8 Master Class features the topic of heterogeneous design and advanced packaging. In this blog I preview why the role of packaging has evolved from simply protecting and connecting chips to circuit boards, to now being a competitive imperative for the world’s leading semiconductor and systems companies.

Not All Semiconductor Innovation Occurs at the Leading Edge

As everyday products like phones and cars get smarter, they demand more silicon, much of which is not leading-edge logic and memory. Applied Materials’ ICAPS group was formed to solve the unique design and manufacturing challenges of devices built using process nodes that are no longer found at the leading edge. In this blog I outline why devices in this segment are experiencing a renaissance of innovation.

Introducing Breakthroughs in Materials Engineering for DRAM Scaling

To help the industry meet global demand for more affordable, high-performance memory, Applied Materials today introduced solutions that support three levers of DRAM scaling: a new hard mask material for capacitor scaling, a low-k dielectric material for the interconnect wiring, and the adoption of high-k metal gate transistors for advanced DRAM designs.

DRAM Scaling Requires New Materials Engineering Solutions

The AI Era of computing is fueling exponential growth in data generation, and the entire technology ecosystem depends on the semiconductor industry finding new ways to scale DRAM architectures to keep pace with bit demand. New hard mask patterning films can enable thinner capacitors with the highest possible aspect ratios, while new dielectric insulating materials can reduce the spacing between metal lines, both resulting in new ways to shrink.