PPAC

Classic Moore’s Law Scaling Challenges Demand New Ways to Wire and Integrate Chips

As classic 2D scaling with EUV shrinks on-chip wiring, electrical resistance increases exponentially, creating power, performance and heat challenges. Moreover, as transistor counts continue to increase exponentially while 2D scaling slows, die sizes are increasing to the point where designers are hitting the “reticle limit” of chip designs. Fortunately, innovations in chip wiring will enable chipmakers to continue delivering improvements in performance and power—while advances in chip integration will give designers virtually unlimited transistor budgets. In short, “new ways to wire and integrate chips” will enable amazing computing experiences for everyone.

Trends Accelerating the Semiconductor Industry in 2021 and Beyond

2020 will be remembered most for the challenges of COVID-19. In the world of technology, it will be remembered for accelerating digital transformations that would have taken many more years to play out. Entering 2021, the dependency between the global economy and semiconductors is greater than it’s ever been. At the same time, the way chips are being made is changing as traditional Moore’s Law scaling slows. Applied Materials is dedicated to driving new ways to help our customers continue to deliver improvements in chip power, performance and cost, in record time.