Patterning

At Applied’s 2021 Logic Master Class held today, the company showcased several innovations that help solve key logic scaling challenges and deliver continued improvements in PPACt™ at 3nm and beyond.

Unless we can solve pattern variability challenges, we won’t be able to further scale logic chips and provide users with simultaneous improvements in power, performance and cost. Innovations in “DTCO” and materials engineering are here to help.

At our upcoming Logic Master Class, experts from Applied and the industry will shed light on the innovations needed to enable advanced logic to further scale and deliver improvements in PPACt. In this blog I give a preview of what we’ll be discussing related to transistor design and scaling challenges.

My latest blog describes three innovative patterning techniques that complement EUV and accelerate the industry’s roadmap for logic and DRAM scaling.

Join Applied Materials at the 2019 SPIE Advanced Lithography Symposium as we present our latest R&D advancements on layer-to-layer alignment, defect detection and 3D pattern characterization, and highlight new e-beam technology.

At this year’s SPIE symposium Applied Materials will present several technical papers focused on solving some of the industry’s toughest patterning challenges.

Patterning challenges for the semiconductor industry are growing as the number of multi-patterned layers being used in the 10nm and beyond nodes increase.