Patterning

The patterning challenges of today’s most advanced logic and memory chips can be solved with a new playbook that takes the industry from optical target-based approximation to actual, on-device measurements; limited statistical sampling to massive, across-wafer sampling; and single-layer patterning control to integrative multi-layer control. Applied’s new PROVision® 3E system is designed to enable this new playbook.

As the semiconductor industry increasingly moves from simple 2D chip designs to complex 3D designs based on multipatterning and EUV, patterning control has reached an inflection point. The optical overlay tools and techniques the semiconductor industry traditionally used to reduce errors are simply not precise enough for today’s leading-edge logic and memory chips.

At Applied’s 2021 Logic Master Class held today, the company showcased several innovations that help solve key logic scaling challenges and deliver continued improvements in PPACt™ at 3nm and beyond.

Unless we can solve pattern variability challenges, we won’t be able to further scale logic chips and provide users with simultaneous improvements in power, performance and cost. Innovations in “DTCO” and materials engineering are here to help.

At our upcoming Logic Master Class, experts from Applied and the industry will shed light on the innovations needed to enable advanced logic to further scale and deliver improvements in PPACt. In this blog I give a preview of what we’ll be discussing related to transistor design and scaling challenges.

My latest blog describes three innovative patterning techniques that complement EUV and accelerate the industry’s roadmap for logic and DRAM scaling.

Join Applied Materials at the 2019 SPIE Advanced Lithography Symposium as we present our latest R&D advancements on layer-to-layer alignment, defect detection and 3D pattern characterization, and highlight new e-beam technology.

At this year’s SPIE symposium Applied Materials will present several technical papers focused on solving some of the industry’s toughest patterning challenges.

Patterning challenges for the semiconductor industry are growing as the number of multi-patterned layers being used in the 10nm and beyond nodes increase.