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Unless we can solve pattern variability challenges, we won’t be able to further scale logic chips and provide users with simultaneous improvements in power, performance and cost. Innovations in “DTCO” and materials engineering are here to help.
At our upcoming Logic Master Class, experts from Applied and the industry will shed light on the innovations needed to enable advanced logic to further scale and deliver improvements in PPACt. In this blog I give a preview of what we’ll be discussing related to transistor design and scaling challenges.
Join Applied Materials at the 2019 SPIE Advanced Lithography Symposium as we present our latest R&D advancements on layer-to-layer alignment, defect detection and 3D pattern characterization, and highlight new e-beam technology.