Moore's Law

Classic Moore’s Law Scaling Challenges Demand New Ways to Wire and Integrate Chips

As classic 2D scaling with EUV shrinks on-chip wiring, electrical resistance increases exponentially, creating power, performance and heat challenges. Moreover, as transistor counts continue to increase exponentially while 2D scaling slows, die sizes are increasing to the point where designers are hitting the “reticle limit” of chip designs. Fortunately, innovations in chip wiring will enable chipmakers to continue delivering improvements in performance and power—while advances in chip integration will give designers virtually unlimited transistor budgets. In short, “new ways to wire and integrate chips” will enable amazing computing experiences for everyone.

WFE Intensity Step-up: 3D NAND Case Study

We’ve received great feedback on our “Battle of Exponentials” framework, which examines the market impacts we’ve observed since around 2015 as data generation continued to expand at an exponential rate while classic Moore’s Law scaling slowed. In this blog post we focus on the step-up in NAND equipment capital intensity that occurred during the transition from 2D to 3D NAND architectures.

The Fourth Era of Computing Needs More than Advanced Logic and Memory Chips

At the Applied Materials Master Class today, we highlight two fast-growing and highly enabling areas of the semiconductor industry. “ICAPS” silicon powers billions of new devices on the edge—including electric vehicles. No longer an afterthought, packaging now enables the benefits associated with Moore’s Law to continue even as 2D scaling slows. Today’s class demonstrates that the AI Era requires innovation across a wide range of technologies, from the edge to the cloud.

Heterogeneous Design and Advanced Packaging Enable Advances in PPACt™ Even as Classic Moore’s Law Scaling Slows

Applied’s upcoming, Sept. 8 Master Class features the topic of heterogeneous design and advanced packaging. In this blog I preview why the role of packaging has evolved from simply protecting and connecting chips to circuit boards, to now being a competitive imperative for the world’s leading semiconductor and systems companies.