sparse sampling on a wafer

Innovations in eBeam Metrology Enable a New Playbook for Patterning Control

The patterning challenges of today’s most advanced logic and memory chips can be solved with a new playbook that takes the industry from optical target-based approximation to actual, on-device measurements; limited statistical sampling to massive, across-wafer sampling; and single-layer patterning control to integrative multi-layer control. Applied’s new PROVision® 3E system is designed to enable this new playbook.

Breakthrough in Metrology Needed for Patterning Advanced Logic and Memory Chips

As the semiconductor industry increasingly moves from simple 2D chip designs to complex 3D designs based on multipatterning and EUV, patterning control has reached an inflection point. The optical overlay tools and techniques the semiconductor industry traditionally used to reduce errors are simply not precise enough for today’s leading-edge logic and memory chips.

Designing “Eyes” into Process Equipment to Improve Chip Performance and Yield

Metrology allows process engineers to see the results of process steps. Today, driving improvements in chip performance, power and area/cost (PPAC) requires novel architectures and exotic material stacks. This is introducing new sources of atomic-scale variation that can negatively impact chip performance and yield. It is becoming imperative to “watch” the deposition process as it occurs to control variability and deliver repeatable performance.