logic

In this blog I illustrate how the semiconductor revenue CAGR has increased in recent years and explain why growth could continue at this higher rate for the foreseeable future.

At Applied’s 2021 Logic Master Class held today, the company showcased several innovations that help solve key logic scaling challenges and deliver continued improvements in PPACt™ at 3nm and beyond.

Unless we can solve pattern variability challenges, we won’t be able to further scale logic chips and provide users with simultaneous improvements in power, performance and cost. Innovations in “DTCO” and materials engineering are here to help.

While transistor performance improves with scaling, the same cannot be said for interconnects. In fact, interconnect resistance increases as we move to smaller process nodes, which compromises device performance and power consumption. To continue scaling interconnects in advanced logic requires innovations in materials engineering.

At our upcoming Logic Master Class, experts from Applied and the industry will shed light on the innovations needed to enable advanced logic to further scale and deliver improvements in PPACt. In this blog I give a preview of what we’ll be discussing related to transistor design and scaling challenges.

My latest blog describes three innovative patterning techniques that complement EUV and accelerate the industry’s roadmap for logic and DRAM scaling.

Amid a slowdown in classic Moore’s Law scaling, heterogeneous design and advanced packaging play a growing role in the logic roadmap.

Our latest in a series of blogs inspired by Applied Materials’ panel discussion at IEDM explores where and how data should be processed and stored to drive computing efficiency while curbing energy consumption.

Applied Materials moderated a thought-provoking panel discussion during IEDM which showed that while there is no single path to achieving continued improvements in chip performance, power and area-cost, the industry will be well-served to search for solutions together.