logic

At our upcoming Logic Master Class, experts from Applied and the industry will shed light on the innovations needed to enable advanced logic to further scale and deliver improvements in PPACt. In this blog I give a preview of what we’ll be discussing related to transistor design and scaling challenges.

My latest blog describes three innovative patterning techniques that complement EUV and accelerate the industry’s roadmap for logic and DRAM scaling.

Amid a slowdown in classic Moore’s Law scaling, heterogeneous design and advanced packaging play a growing role in the logic roadmap.

Our latest in a series of blogs inspired by Applied Materials’ panel discussion at IEDM explores where and how data should be processed and stored to drive computing efficiency while curbing energy consumption.

Applied Materials moderated a thought-provoking panel discussion during IEDM which showed that while there is no single path to achieving continued improvements in chip performance, power and area-cost, the industry will be well-served to search for solutions together.

What’s clear from the panel discussion I recently moderated with Facebook, IBM, Intel, Stanford and TSMC is that the semiconductor design and manufacturing model is evolving and will look extremely different in the years ahead.

Join us on Dec. 10 in San Francisco as we discuss new ways of improving chip performance, power and area-cost beyond traditional Moore’s Law scaling.