Classic Moore’s Law Scaling Challenges Demand New Ways to Wire and Integrate Chips

As classic 2D scaling with EUV shrinks on-chip wiring, electrical resistance increases exponentially, creating power, performance and heat challenges. Moreover, as transistor counts continue to increase exponentially while 2D scaling slows, die sizes are increasing to the point where designers are hitting the “reticle limit” of chip designs. Fortunately, innovations in chip wiring will enable chipmakers to continue delivering improvements in performance and power—while advances in chip integration will give designers virtually unlimited transistor budgets. In short, “new ways to wire and integrate chips” will enable amazing computing experiences for everyone.

Introducing Breakthroughs in Materials Engineering for DRAM Scaling

To help the industry meet global demand for more affordable, high-performance memory, Applied Materials today introduced solutions that support three levers of DRAM scaling: a new hard mask material for capacitor scaling, a low-k dielectric material for the interconnect wiring, and the adoption of high-k metal gate transistors for advanced DRAM designs.

DRAM Scaling Requires New Materials Engineering Solutions

The AI Era of computing is fueling exponential growth in data generation, and the entire technology ecosystem depends on the semiconductor industry finding new ways to scale DRAM architectures to keep pace with bit demand. New hard mask patterning films can enable thinner capacitors with the highest possible aspect ratios, while new dielectric insulating materials can reduce the spacing between metal lines, both resulting in new ways to shrink.