DRAM

To help the industry meet global demand for more affordable, high-performance memory, Applied Materials today introduced solutions that support three levers of DRAM scaling: a new hard mask material for capacitor scaling, a low-k dielectric material for the interconnect wiring, and the adoption of high-k metal gate transistors for advanced DRAM designs.

The AI Era of computing is fueling exponential growth in data generation, and the entire technology ecosystem depends on the semiconductor industry finding new ways to scale DRAM architectures to keep pace with bit demand. New hard mask patterning films can enable thinner capacitors with the highest possible aspect ratios, while new dielectric insulating materials can reduce the spacing between metal lines, both resulting in new ways to shrink.

My latest blog describes three innovative patterning techniques that complement EUV and accelerate the industry’s roadmap for logic and DRAM scaling.

Applied Materials convened a panel of industry experts to explore trends and challenges for memory technology over the next decade—from continued scaling of mainstream technologies to developing new memory and computing architectures for Big Data and Artificial Intelligence.

Join Applied Materials and a panel of experts in San Francisco on Dec. 4 to explore the types of memories needed for artificial intelligence applications.

The industry's first extreme selectivity etch tool introduces new materials engineering capabilities for the next generation of self-aligned patterning schemes and future scaling of 3D logic and memory chips.

In the same way that various prophets of doom foretell the imminent demise of Moore’s Law, we often hear that conventional memory technologies are going to run out of steam soon. However, the semiconductor industry is highly-skilled at extending its existing architectures rather than making the leap to shiny new ones with apparently compelling advantages. Thus, incremental advances in conventional technology have delayed the introduction of a raft of exciting new memory technologies. When will the tipping point be reached that pushes one or more into the mainstream? Read what the some of the best-informed minds in the business have to say after the jump. 

Mobile computing is now everywhere, more than ever before as a result of faster and more capable smart phones, tablets, and laptops.Universal mobility and instant-on connectivity may herald a new era in computing, but improvements in key technologies are necessary if we are going to keep up with consumers’ constant demand for higher performance, longer battery life and ultra-sleek profiles.To address these technology improvements and answer key questions that may significantly impact the way we interface with an increasingly connected world, Applied Ventures and the MIT Club of Northern California (MITCNC) will host a lively panel discussion with innovators from across the memory value chain on Wednesday, February 1 at 6:30pm in Santa Clara, Calif.[edit: you can read a report from the session here.]

It's not just movies, televisions and video games that are going three-dimensional these days. Microchips are doing it, too.Semiconductors aren't shifting into the third dimension because it’s fashionable, though. This shift is about continuing Moore’s Law, the relentless drive for higher performance that has driven the industry for four decades.With three very different types of 3D construction in development today, it can be a confusing subject. Vertical chip structures, 3D device stacking, 3D chip packaging – what does it all mean?We made this video to help demystify the subject. Did it help? Let me know in the comments below.