copper

Improving logic device power and performance as critical dimensions scale requires materials innovation at the lower level interconnects—and Integrated Materials Solutions can accelerate customer success.

The Endura® system is recognized as the most successful metallization tool in the history of the semiconductor industry. Since its introduction, through continuous infusions of new innovations and process technologies, it has enabled customers to advance Moore’s Law from the .75 micron node to today’s sub-20 nanometer nodes, and can continue beyond to sub-10 nanometer designs.To appreciate what made the Endura a truly landmark system, and how the value it provides has been sustained over decades, I'd like to reference the recent VLSIresearch feature and highlight some key points.

This TEM image taken at Applied Materials’ Maydan Technology Center shows a series of 20nm-wide trenches in cross section.  These tiny structures – about 1/5000th of the diameter of an average human hair – are similar to the interconnects used to wire the billions of transistors in next-generation microchips.  You can see that each trench is partially filled with copper, all the way to the bottom, with no gaps or voids.  This was achieved using Applied’s revolutionary copper reflow technology.  For a primer on how interconnects are made and how copper reflow works, see this video.

Given that today’s advanced chips can contain billions of transistors, 60 miles of copper wiring and 10 billion vertical connections between metal layers, the challenges and potential pitfalls this level of complexity presents are mind-boggling. One major problem on the horizon at 20nm and below is the threat of voids forming in the vertical interconnects commonly called vias.

If you were to slice up a microchip and take a look (you’d need a really powerful microscope, I'm afraid) you would see what looks like a nanoscale layer cake.All the active circuit elements – transistors, memory cells etc. – are on the bottom. The other 90% of the chip is a maze of tiny copper wires, which we call interconnects.The history of chip development is all about shrinking circuit features. When the transistors shrink, so must the interconnects. Today, the smallest interconnects can be  fewer than 200 atoms across.In this video, I take a quick look at how the interconnect fabrication process is done and then demonstrate how our revolutionary copper reflow technology works.

Applied Materials’ Bob Linke, process integration manager, Semitool Business Unit, discusses the Applied Raider GT electrochemical deposition (ECD) system – a significant innovation for fabricating copper interconnects at the 22nm technology node and beyond.For more technical information on the Raider GT system and Applied's other new technologies for advanced chipmaking, visit www.becauseinnovationmatters.com.