Advanced Packaging

Classic Moore’s Law Scaling Challenges Demand New Ways to Wire and Integrate Chips

As classic 2D scaling with EUV shrinks on-chip wiring, electrical resistance increases exponentially, creating power, performance and heat challenges. Moreover, as transistor counts continue to increase exponentially while 2D scaling slows, die sizes are increasing to the point where designers are hitting the “reticle limit” of chip designs. Fortunately, innovations in chip wiring will enable chipmakers to continue delivering improvements in performance and power—while advances in chip integration will give designers virtually unlimited transistor budgets. In short, “new ways to wire and integrate chips” will enable amazing computing experiences for everyone.
Applied Materials

Opportunities in Through-Silicon Via Technology for 3D Packaging

The industry has reached a crucial inflection point on the adoption and commercialization of 3D packaging technology, and Applied Materials’ CTO Hans Stork gave attendees of the 3D Architectures for Semiconductor Integration and Packaging conference held recently in Burlingame, Calif. his assessment on the current status of this emerging technology.According to Stork, though significant challenges remain with vertical interconnects using through-silicon vias (TSVs), the semiconductor industry is on the verge of turning this into a manufacturing technology.