3D

sparse sampling on a wafer

Innovations in eBeam Metrology Enable a New Playbook for Patterning Control

The patterning challenges of today’s most advanced logic and memory chips can be solved with a new playbook that takes the industry from optical target-based approximation to actual, on-device measurements; limited statistical sampling to massive, across-wafer sampling; and single-layer patterning control to integrative multi-layer control. Applied’s new PROVision® 3E system is designed to enable this new playbook.
The Revolutionary Impact of 3D Chip Packaging

The Revolutionary Impact of 3D Chip Packaging

Personal mobile devices like smartphones, tablets and laptop PCs are rapidly evolving, becoming faster, smaller and functionally more sophisticated. To maintain this dramatic progress in device capability, the semiconductor industry is now at a new inflection point – the era of 3D chip packaging.In this video, Applied’s Sesh Ramaswami discusses the fundamentals of advanced packaging and the revolutionary impact this technology is having on the gadgets we buy and the cloud infrastructure that makes mobility work.
Applied Materials

Supply Chain Collaboration for 3D Interconnect Applications

3D Interconnect applications are attracting more and more interest from a large number of players in the semiconductor industry. I recently participated in two conferences (IWLPC – International Wafer Level Packaging Conference and IMAPS- International Microelectronics and Packaging Society Conference) on this topic to keep up-to-date on the new activities and developments in the industry and to share our latest advancements achieved with EMC3D consortium.