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Semiconductors

Newer Ways to Shrink

by Uday Mitra, Ph.D.
Apr 19, 2022
The industry will continue to use EUV lithography and materials engineering to push logic density scaling to the limit. In recent years, DTCO techniques have supplemented classic 2D scaling, and today, these “newer ways to shrink” contribute about half of the industry’s progress.
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Semiconductors

New Ways to Shrink: Further EUV Scaling Depends on Materials Engineering and Metrology Breakthroughs

by Regina Freed
Apr 14, 2022
Classic 2D Moore’s Law scaling can continue for years into the future—as long as we also solve the materials engineering and metrology challenges that accompany EUV lithography.
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Corporate

Applied Materials Earns Intel’s 2022 EPIC Outstanding Supplier Award with Supplier Diversity Distinction

by Applied Materials Blog
Apr 07, 2022
The Intel EPIC Outstanding Supplier Award recognizes the highest level of achievement in the Intel global supply chain and is an ongoing realization of continuous improvement within the high-performing Intel supplier ecosystem. In 2022, only six suppliers across the Intel supply chain earned an Intel Outstanding Supplier Award, making them truly the best of the best.
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Reducing Yield Loss with Seam-Suppressed Tungsten Contact Gap Fill
Semiconductors

Reducing Yield Loss with Seam-Suppressed Tungsten Contact Gap Fill

by Jonathan Bakke
Jun 23, 2016
Applied has introduced a new method of tungsten gap fill for logic contacts and local interconnects that will help improve the yield of next-generation devices. Learn why it’s so significant.
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Overcoming Contact Resistance in Next-Generation Devices
Semiconductors

Overcoming Contact Resistance in Next-Generation Devices

by Jonathan Bakke
Jun 16, 2016
New materials engineering innovations significantly reduce contact resistance, making it possible to extend tungsten metallization to next-generation devices.
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Overcoming RC in Memory Scaling
Semiconductors

Overcoming RC in Memory Scaling

by Rajkumar Jakkaraju
Jun 02, 2016
New solutions to building DRAMs based on innovations in materials engineering that overcome scaling challenges. 
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Contact Resistance and its Role in Limiting Transistor Performance
Semiconductors

Contact Resistance and its Role in Limiting Transistor Performance

by Jonathan Bakke
Jun 01, 2016
This post examines why contact resistance is becoming a major factor limiting transistor performance as logic devices continue to scale downward.
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Announcing our IT Supplier of the Year
Corporate

Announcing our IT Supplier of the Year

by Glaston Ford
May 31, 2016
Cisco's partnership, support and continuous delivery of new innovations have earned the company the Applied Materials IT Supplier of the Year Award.
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RC Delay – Bottleneck to Scaling
Semiconductors

RC Delay – Bottleneck to Scaling

by Rajkumar Jakkaraju
May 24, 2016
In this blog post, I discuss why RC delay is a major issue in the continued downward scaling of logic and memory devices. 
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Examining Emerging Memory Technologies and 3D Architectures at IITC
Semiconductors

Examining Emerging Memory Technologies and 3D Architectures at IITC

by Dr. Er-Xuan Ping
May 23, 2016
A review of the integration and high-volume manufacturing challenges of new memories to be discussed at IITC this week.
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Applied Materials Hosts Memory Panel Discussion at IEEE IMW
Semiconductors

Applied Materials Hosts Memory Panel Discussion at IEEE IMW

by Gill Lee
May 04, 2016
Applied Materials is chairing a panel discussion with memory technology leaders including Intel, Samsung, SK hynix and Western Digital to address new types of storage class memory as part of the eighth IEEE International Memory Workshop on May 16. 
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Applied Materials Named to 100 Best Corporate Citizens List
Corporate Responsibility

Applied Materials Named to 100 Best Corporate Citizens List

by Applied Materials Blog
Apr 26, 2016
Applied Materials once again placed on Corporate Responsibility Magazine’s 100 Best Corporate Citizens List for outstanding CSR performance. 
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