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At our upcoming Logic Master Class, experts from Applied and the industry will shed light on the innovations needed to enable advanced logic to further scale and deliver improvements in PPACt. In this blog I give a preview of what we’ll be discussing related to transistor design and scaling challenges.
We are at the beginning of a new technological era for the field of optics. To accelerate the commercialization of Flat Optics, a larger collaborative effort is needed to scale the technology and deliver its full benefits to a wide range of applications.
To help the industry meet global demand for more affordable, high-performance memory, Applied Materials today introduced solutions that support three levers of DRAM scaling: a new hard mask material for capacitor scaling, a low-k dielectric material for the interconnect wiring, and the adoption of high-k metal gate transistors for advanced DRAM designs.
Applied Materials’ latest Sustainability Report outlines the company’s forward-looking objectives and recaps the significant and wide-ranging progress made on our sustainability journey during the past year.
Recently I participated in a fascinating panel discussion with experts from Arm, Google, Intel, Microsoft, UC Santa Barbara and VMware to explore how Big Data, AI and cloud computing can be used to help mitigate—rather than contribute to—climate change.
Watch the video replay of Applied Materials CEO Gary Dickerson’s keynote at SEMICON West to hear about new initiatives Applied is driving to enable a more sustainable company, industry and world.
Applied’s newest Integrated Materials Solution solves the challenge of selective tungsten deposition, enabling simultaneous improvements in chip power, performance and area/cost (PPAC) in the most advanced foundry-logic nodes.
With EUV-enabled advances in 2D scaling pushing the limits of conventional materials engineering techniques, a breakthrough is needed to overcome increases in contact resistance and enable continued improvements in chip performance, power and area/cost (PPAC).
The advent of EUV lithography is helping overcome transistor scaling challenges, but new innovations in materials engineering are needed to enable performance and power to scale as well.
