We are in awe of the arts groups and their leaders whose tremendous creativity and clever use of technology brought artists and audiences together for powerful, entertaining, engaging experiences all while we sheltered in place.

At Applied’s 2021 Logic Master Class held today, the company showcased several innovations that help solve key logic scaling challenges and deliver continued improvements in PPACt™ at 3nm and beyond.

Unless we can solve pattern variability challenges, we won’t be able to further scale logic chips and provide users with simultaneous improvements in power, performance and cost. Innovations in “DTCO” and materials engineering are here to help.

While transistor performance improves with scaling, the same cannot be said for interconnects. In fact, interconnect resistance increases as we move to smaller process nodes, which compromises device performance and power consumption. To continue scaling interconnects in advanced logic requires innovations in materials engineering.

At our upcoming Logic Master Class, experts from Applied and the industry will shed light on the innovations needed to enable advanced logic to further scale and deliver improvements in PPACt. In this blog I give a preview of what we’ll be discussing related to transistor design and scaling challenges.

We are at the beginning of a new technological era for the field of optics. To accelerate the commercialization of Flat Optics, a larger collaborative effort is needed to scale the technology and deliver its full benefits to a wide range of applications.

To help the industry meet global demand for more affordable, high-performance memory, Applied Materials today introduced solutions that support three levers of DRAM scaling: a new hard mask material for capacitor scaling, a low-k dielectric material for the interconnect wiring, and the adoption of high-k metal gate transistors for advanced DRAM designs.

The AI Era of computing is fueling exponential growth in data generation, and the entire technology ecosystem depends on the semiconductor industry finding new ways to scale DRAM architectures to keep pace with bit demand. New hard mask patterning films can enable thinner capacitors with the highest possible aspect ratios, while new dielectric insulating materials can reduce the spacing between metal lines, both resulting in new ways to shrink.

During Applied’s annual EarthWorks campaign, employees across the globe are encouraged to learn about and take action dedicated to environmental sustainability.