3D NAND: The Future of Flash

With the 5th Annual International Memory Workshop (IMW) coming up next week in Monterey, CA I wanted to point out a recent article from Semiconductor Manufacturing & Design.  As the cell-to-cell interference issues characteristic of sub-20nm manufacturing processes threaten to keep NAND from moving to smaller nodes, the major players in the NAND flash market are looking at different approaches to implementing NAND in a 3D chip architecture. The article provides a great summary of the different approaches to 3D NAND customers are adopting and when to expect those technologies to hit the market.

Regardless of which 3D technology a customer uses for NAND production, it’s exciting to note that because 3D NAND uses multiple layers to support bit growth, it doesn’t require the use of more costly technologies. 3D NAND fabs can be built using existing 193nm lithography, which will provide big cost saving to customers and, ultimately, end users purchasing electronic devices using 3D NAND flash.

I will chair a NAND session and poster session at IMW.  The discussion at IMW promises to be a great resource for engineers working with NAND flash to better understand what’s coming up in 3D NAND flash development. There will be also a panel covering STT-MRAM, which will cover the most recent progresses in the STT-MRAM development.  

Hope to see you there!

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