Overcoming Shallow Trench Isolation Challenges for Sub-20 Nanometer

Jun142013

To prevent electrical current leaking between adjacent transistors, state-of-the-art microchips feature shallow trench isolation (STI) to isolate transistors from each other. Key steps in the STI process involve etching a pattern of trenches in the silicon, depositing dielectric materials to fill the trenches, and removing the excess dielectric using technologies such as chemical-mechanical planarization (CMP). But as the industry scales to sub-20 nanometers significant challenges for the STI etch step are emerging.

For optimal transistor performance and desired yield — two of the industry’s most important metrics, controlling critical dimension (CD) of the lines and trench depth are essential.  Exacerbating these requirements at sub-20 nanometers are trench aspect ratios as high as 20:1, and increasing trench CD width variations stemming from double patterning.  Due to the aspect ratio dependent etching effect, CD variations can lead to non-uniform trench depths resulting in potential performance and yield hits.

Across-wafer uniformity and profile control at the wafer’s edge are additional STI challenges for etch technology.  This is due to the edge area being prone to discontinuities of the materials along with shifts in electrical and thermal properties.  Why is the edge area so important? It’s because it accounts for over 10% of yielding devices.

The most recent issue to emerge for sub-20 nanometer STI etching is a tendency for pattern or line collapse, especially after wet cleaning.  While pattern collapse has been an on-going issue given the weak mechanical strength (Young’s modulus) of lithography resist films, pattern collapse has been mostly immune for STI thanks to the relative rigidity of silicon materials.  At sub-20 nanometer we’re seeing this change and preventing collapse is becoming more challenging with significant implications for yield. 

Applied technologists recently examined these STI etch challenges in an experimental study using an Applied inductively coupled plasma silicon etcher.  The results along with a review of some general guidelines for overcoming the troublesome issues are presented in a technical paper published in the June issue of Solid State Technology.  I invite you to read the feature article on the Solid State Technology web site.

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