Semiconductors

Designing “Eyes” into Process Equipment to Improve Chip Performance and Yield

Metrology allows process engineers to see the results of process steps. Today, driving improvements in chip performance, power and area/cost (PPAC) requires novel architectures and exotic material stacks. This is introducing new sources of atomic-scale variation that can negatively impact chip performance and yield. It is becoming imperative to “watch” the deposition process as it occurs to control variability and deliver repeatable performance.

Highlights from a Successful #AIDesignForum 2019

Leading technology CEOs and industry thought leaders from across the computing ecosystem convened in San Francisco earlier this week at the second AI Design Forum™ to discuss the future of computing—from materials to systems. What was made clear from the thought-provoking keynotes and many sideline discussions is that AI and Big Data create tremendous growth opportunities for the industry, but to realize their potential requires new levels of innovation.