Semiconductors

Designing “Eyes” into Process Equipment to Improve Chip Performance and Yield

Metrology allows process engineers to see the results of process steps. Today, driving improvements in chip performance, power and area/cost (PPAC) requires novel architectures and exotic material stacks. This is introducing new sources of atomic-scale variation that can negatively impact chip performance and yield. It is becoming imperative to “watch” the deposition process as it occurs to control variability and deliver repeatable performance.