Reducing Yield Loss with Seam-Suppressed Tungsten Contact Gap Fill

In my previous two blog posts (Overcoming Contact Resistance in Next-Generation Devices and Contact Resistance and its Role in Limiting Transistor Performance), I focused on the issue of contact resistance at advanced nodes and how innovations in materials engineering are helping to relieve that scaling challenge. Now I’d like to focus on the challenge of yield loss that accompanies contact scaling.

At earlier nodes, larger dimensions made tungsten (W) fill possible using nucleation followed by conformal CVD deposition. Now, the tops of the ultra-small openings to the plug are prone to overhang, so the conformal process in which the film grows equally on the surface field closes or pinches off the opening before filling is completed, leaving voids. Even in the absence of voids, center seams are an inevitable result of conformal deposition as the fill grows from the sidewalls.

These attributes render extremely small features vulnerable to being breached during CMP allowing the CMP slurry to enter and damage the W plug. This results in high resistance or complete failure of an interconnect that transistors depend on to conduct signals. High feature densities and lack of via redundancy in advanced chip designs mean that a single void can cause complete device failure and significant yield loss (Fig. 1).

Fig. 1. The plot shows yield loss on the y axis vs. defect levels on the x axis. One failure in a billion can cause a yield loss of more than 15% at the 20nm node and even greater losses at smaller nodes.

Our new approach employs a unique “selective” suppression mechanism that produces a bottom-up fill free of seams or voids. Pre-treating the nucleation layer particularly at the upper field creates preferred W growth from the bottom of the structure upwards, minimizing the likelihood of voids caused by feature pinch-off and suppressing the formation of seams.

This seam-suppress tungsten (SSW) gap-fill process optimizes the volume of W and creates more robust features for post-fill integration. In so doing, it relaxes requirements on CMP and dielectric etch steps, thus delivering performance, device design and yield benefits.

Learn more about the Centura iSprint ALD/CVD SSW on our website.

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