RC Delay – Bottleneck to Scaling


R = resistance--the difficulty an electrical current has in passing through a conducting material.

C = capacitance--the degree to which an insulating material holds a charge.

RC delay = the delay in signal speed through the circuit wiring as a result of these two effects.

RC delay is important because it can become a significant obstacle to continued downward scaling of logic and memory devices that drive the performance of today’s multi-functional, mobile consumer electronic devices. Here’s why:

Active devices (transistors) in both logic and memory chips are electrically connected to each other and other areas of the chip with metal wiring. These wires are separated from each other using non-conducting (insulating) dielectric layers. In both logic and memory, the role of interconnects is to transmit signals from one area of the chip to another. The ability to do this as rapidly as possible, while minimizing signal losses in shrinking geometries, is critical for device scaling.

In logic, scaling implies area scaling, that is packing more and more circuits into a smaller area by means of materials and design innovations. In price-sensitive DRAM fabrication, costs must be aggressively controlled, so scaling focuses on obtaining progressively better performance from existing materials and design.

Wire resistance and capacitance both play an important role in determining the speed with which signals are transmitted in a logic or memory circuit.

Where does RC delay come into play?

In general, the speed of signal propagation in logic and memory wires is governed by the same basic principles and depends on the product of resistance and capacitance (RC). Lowering both resistance and capacitance would be ideal. However, the costs of developing and integrating lower-capacitance insulating materials into the fabrication flow are especially high for memory manufacturers. Lowering resistance is therefore the preferred approach for scaling performance.

Different solutions are needed to address the RC challenge, depending on whether the charge travels vertically across different levels of wiring or laterally along the length of the conductor. In either case, the goal is to minimize the resistance of the metal wiring.

In the vertical dimension, solutions are aimed at minimizing interface resistance. Electrical contacts connect the active region of the device to the first level of metal wiring. A semiconductor-to-metal interface (or Ohmic contact) forms the junction between the active region and the metal contact. The objective is to ensure that an electrical charge can travel from the active region through the contact to the upper levels of wiring, and back again. To achieve rapid and maximal charge transmission across the Ohmic contact, a low-resistivity material is formed. Low-resistivity Co silicide has been adopted as the industry standard for this purpose; its effectiveness relies on the deposition of a uniform layer to form a robust Ohmic contact.

In the lateral dimension, solutions are aimed at optimizing the conductivity of the metal forming the wire. Line resistance, as it is called, is a function of both wire dimensions (width, height, length) and the specific properties of the material used to fabricate the wire–typically tungsten or copper.

The easiest means of lowering line resistance would be to increase the volume of the conducting metal (i.e., make the wires wider and taller). However, wider wires restrict scaling and taller wires increase capacitance and pose greater etch challenges. Consequently, lowering wire resistance in leading-edge devices focuses on improving the properties of the conducting material.

In my next blog post, I’ll discuss how to overcome RC delay in memory scaling.