Chip makers and equipment suppliers are taking new steps forward in exploring revolutionary materials and techniques needed to continue enabling breakthroughs in microchip performance. The pace of innovation is ramping at a rate never-before experienced in the industry. We’re going to see more changes in the next five years than we’ve seen in last 15. Without these efforts, the innovation engine that has produced generation after generation of mobility and computing devices capable of astonishing capabilities will stall. One area where disruptive change is coming is the interconnect.
Following is a short explanation of this transition.
Transistors keep getting smaller and faster to maintain the historic pace of Moore’s Law. But what about the interconnect circuitry that connects the billions of transistors on a chip? There's no point making transistors faster if the interconnects can't keep up. Interconnect wiring has shrunk drastically as chip dimensions scale. But as interconnects gets smaller, electrical resistance and capacitance increase, hindering performance. | Click to enlarge
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Resistance is expected to increase 40X from the 20nm to 7/5nm node making it a potential limiting issue. At this point, alleviating the magnitude of resistivity will require fundamental disruptive changes to move the interconnect forward. Reducing capacitance is the other must for increasing circuit performance and controlling power leakage. Changing the insulating material that surrounds and supports the interconnect structure to lower-dielectric-constant materials addresses this issue. | ASIC Cross-Section | |
Today, the copper lines are surrounded with liner and barrier layers that prevent copper atoms from migrating into the surrounding dielectric. These layers are essential for reliability, but they inevitably reduce the cross-sectional area of each wire. To maximize the volume of copper, researchers are considering doing away with liner and barrier layers, instead developing new dielectric materials that incorporate these functions. This change will mark the beginning of the end of the dual damascene interconnect technique used for almost 20 years. Today, the copper lines are surrounded with liner and barrier layers that prevent copper atoms from migrating into the surrounding dielectric. These layers are essential for reliability, but they inevitably reduce the cross-sectional area of each wire. To maximize the volume of copper, researchers are considering doing away with liner and barrier layers, instead developing new dielectric materials that incorporate these functions. This change will mark the beginning of the end of the dual damascene interconnect technique used for almost 20 years. |  | |
| Even with new dielectric materials, dual damascene techniques cannot make reliable copper wires at ~5nm. Small copper grain size means depositing multiple grains which cause electrons to scatter off the many surfaces. Perfectly filling these tiny gaps less than a hundred atoms across is a further challenge. A single gap, or void, can cripple chip performance. New integration schemes that eliminate the issue of copper gap fill are being considered. |
Source: NVIDIA Corporation 2011 | |
Eventually copper will be retired entirely. At 3nm, there are simply too many performance problems to overcome:
As yet, there is no clear substitute candidate for copper, and given how long the R&D process in chip making is time is running short. |  |
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