Parametric Characterization of TSVs
Paving the way for the manufacture of 3D-integrated stacked chips, technologists and engineers at Applied Materials have recently completed electrical characterization of through-silicon via (TSV) structures. This development is vitally important since TSVs are the vertical interconnections that carry power and high-bandwidth speed signals between the stacked die of layered logic and memory devices.
The critical functions performed by TSVs require thorough mechanical and electrical characterization. Important considerations include:
- Stress impact of the relatively large TSVs on FinFET performance
- Controlling the protrusion of the ends of the copper in the TSV to ensure good electrical contact and avoid failure of current leakage and capacitance from the TSV to the substrate
Electrical characterization and microanalysis of TSV structures (Figure 1) fabricated by a baseline integrated process sequence was performed at Applied’s Maydan Technology Center. Testing was conducted in Santa Clara and in Singapore at the Asia Product Development Center (APDC), a process integration lab equipped with a complete 300mm wafer level packaging (WLP) line. The vias created were 5µm in diameter and 50µm deep. Pitch or center-to-center spacing between TSVs were set at 10µm, 25µm and 50µm. The total number of TSVs was 522, 256, and 240 for the 10µm, 25µm, and 50µm pitches, respectively.
Figure 1. Focused ion beam (FIB) SEM images of TSV structures. FIB images show a 5x50µm TSV: a) overall TSV structure, b) field oxide, and c) TSV sidewall oxide.
TSV capacitance was measured by sweeping the bias voltage from -10V to 10V with a small AC component at 1MHz. The measured capacitance (~ 60fF) conformed to expected values of 5x50μm TSVs at the three different pitches (Figure 2).
Figure 2. TSV Capacitance distribution for three TSV pitches.
Low capacitance is essential to reduce power and minimize crosstalk between neighboring TSVs. Furthermore, it is critical to minimize leakage current from the TSV into the surrounding bulk silicon. It is also a measure of the integrity of the barrier layer that prevents copper from diffusing into silicon, a phenomenon that can lead to reliability problems. Measured leakage per TSV fell within a narrow range and matched data published by M. Stucchi, et al (Figure 3). 
Figure 3. Single TSV leakage current distribution at 5V and 10V bias conditions (leakage matched published data by M. Stucchi, et al. )
To verify the integrity of the oxide-silicon and barrier-oxide interfaces, we imaged the TSVs to ensure no metal had diffused into either the oxide liner or the bulk silicon (Figure 4). The imaging was performed using a specialized electron microscope technique called STEM/EELS which simultaneously gives a visual image and the elemental composition of the sample.
Figure 4. Microanalysis results: (a) TEM image at TSV sidewall; (b) Line-scan HAADF (High-Angle Annular Dark-Field Microscopy) image of the Si-oxide-barrier-Cu interface; (c) HAADF counts of materials; (d) Relative composition of each element.
The findings generally conformed to expectations of robust TSV characteristics and the majority of the TSVs passed electrical tests. These results provide confidence that the necessary elements are in place to manufacture TSVs.
 M. Stucchi, et al., “Capacitance Measurements of Two-Dimensional and Three-Dimensional IC Interconnect Structures by Quasi-Static c-V Technique,” IEEE Trans. Instrum. Meas. Vol. 61, No.7, pp. 1979-1990, 2012.