Opportunities in Through-Silicon Via Technology for 3D Packaging

The industry has reached a crucial inflection point on the adoption and commercialization of 3D packaging technology, and Applied Materials’ CTO Hans Stork gave attendees of the 3D Architectures for Semiconductor Integration and Packaging conference held recently in Burlingame, Calif. his assessment on the current status of this emerging technology.

According to Stork, though significant challenges remain with vertical interconnects using through-silicon vias (TSVs), the semiconductor industry is on the verge of turning this into a manufacturing technology. The drive toward 3D interconnections is being led by smart phones, gaming, and other applications that require high bandwidth between memory and logic. “Smart phones are driving a lot of technology choices these days,” he said adding that small-form-factor gaming also has a huge audience of users that crave the higher graphics capabilities that 3D interconnects can deliver.

While the fundamental manufacturing processes required for through-silicon vias (TSVs) have been established, IC manufacturers are still ironing out design and process recipes. Most of the conference speakers agreed that the thin (50μm) wafers often used for TSV fabrication, pose significant, handling challenges.

Thin wafer handling “remains a yellow, not a green light. We need to pay attention to it.” Bubbles can develop in the adhesives used to bond the active wafer to a silicon or glass carrier. The thin wafers can easily bow, and cracks can develop at the wafer’s edge. “This is an area where we need to see more work in actual fabs, with real process recipes,” Stork said.

Other speakers that put the spotlight on thin wafer handling included Bob Patti, CTO of Tezzaron Semiconductors and a pioneer in the 3D TSV sector, who confirmed “our experience with thin wafer handling has not been that great.” Jan Vardaman, president of packaging consultancy TechSearch International, agreed, “wafer handling is where the yield hits are right now.” Semiconductor companies “are at the stage today where they are doing the real hard engineering work” to bring in TSVs.

Stork highlighted some of the challenging requirements for TSV manufacturing equipment. In the etch process, the creation of high aspect ratio vias required the development of systems that can create smooth-sidewall vias through 50 to 100 microns of silicon, and with precise profile control. Subsequent dielectric deposition processes must cope with relatively low thermal budgets while delivering the desired electrical properties, including minimizing the current leakage. The physical vapor deposition (PVD) process used to deposit barrier/seed layers must be adapted to accommodate customers’ choice of bonded substrates and related temperature management issues.

Stork noted that Applied’s acquisition of electrochemical deposition (ECD) system manufacturer Semitool was largely aimed at exploiting the opportunities in advanced packaging, where cost and performance issues are equally important. “3D interconnects require rapid copper filling of TSVs across the entire wafer, without voids.” Applied’s copper ECD and chemical-mechanical planarization (CMP) tools can be optimized together to ensure complete fill with minimal excess copper (known as overburden), leading to short CMP process times. Accurate, in-situ end point detection technology in the CMP tool is also stops the process at precisely the right moment to avoid potential damage from excess material removal.

In the question and answer period, participants asked about the challenge of inspecting the high-aspect ratio vias. “Inspection and metrology must be implemented, but will require some unique capabilities,” said Stork. Infrared technology may be required to measure the deep vias, and could possibly be integrated on the etch tools. Applied will leverage its advanced brightfield and darkfield inspection technologies to solve metrology challenges with 3D TSVs.

Asked if Applied intends to develop 200mm equipment for the 3D space, the response was that the company is doing some work on 200mm equipment. However, it was pointed out that customers’ 200 mm return on investment is not as good as it is in 300 mm.

Several speakers noted that TSV fabrication must cost no more than $150 per wafer, a target that represents a steep challenge for the industry. “As we learn more about the processes, we can optimize for cost,” Stork said. As Moore’s Law tells us, the semiconductor industry historically excels at reducing cost to enable widespread adoption of advanced technology.

Receive updates in your inbox!

Subscribe Now

Want to join the discussion?

Add new comment:*

* Comments must adhere to our Discussion Guidelines and Rules of Engagement.

You can also fill out this form to contact us directly and we will get back to you.