Interconnect Performance in the Spotlight

Nov292012

Transistors get all the attention these days as the savior of Moore's Law. But there's no point making transistors faster if the wires between them – interconnects – can't keep up.

The 14 nanometer node is expected to be an inflection point for the chip industry, beyond which the resistivity of copper interconnects will increase exponentially and may become a limiting factor in chip design.

The discussion will address critical questions for the semiconductor industry, including the possibility of replacing copper as the material of choice for interconnect structures. If not, will new circuit designs and system architectures be able to address future limitations in interconnect performance? The complexity of multi-patterning and EUV lithography timing may also impact chipmakers' interconnect pitch scaling roadmaps.

Experts from across the industry will provide insights on these critical issues in a panel titled "Interconnect Performance - Overcoming the Impact of Transistor Scaling."

Click here to register for what promises to be an illuminating and lively discussion. We look forward to welcoming you!

 

Introduction:  Klaus Schuegraf, Ph.D.Vice president and chief technology officer, Silicon Systems Group, Applied Materials, Inc.
Panel:  Robert Aitken, Ph.D.Fellow, ARM Holdings, Ltd.
 Jon CandelariaDirector, interconnect and packaging sciences, Semiconductor Research Corp.
 Dinesh Somasekhar, Ph.D.Senior scientist, Intel Corp.
 Zsolt Tokei, Ph.D.Program director, nano interconnects, IMEC
 Mehul Naik, Ph.D.Distinguished member of technical staff, Applied Materials, Inc.
 Douglas Yu, Ph.D.Senior director, backend R&D, TSMC, Ltd.
 David Lammers (moderator)Contributing editor, SemiMD.com
Where:  Hotel Nikko
222 Mason Street, San Francisco, CA 94102
When:  Tuesday, December 11, 2012
Schedule:  5:00pm - 6:15pmRegistration and Reception
 6:15pm - 7:40pmPanel Discussion
 7:40pm - 8:00pmBeverages/Social

 

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