Innovations for Transistor Scaling at PRiME 2016

Sep292016

Applied Materials will be presenting in five sessions at PRiME 2016, one of the largest international research conferences, being held October 2-7 in Honolulu, Hawaii. This important conference hosted by the Electrochemical Society (ECS), the Electrochemical Society of Japan (ECSJ) and the Korean Electrochemical Society (KECS) is convened every four years. Applied’s talks will focus on inflections in transistor scaling, in particular the epitaxy technologies and materials innovations required for manufacturing advanced devices.
 
One historic change that has taken place in transistor design to address device scalability is the move to the multi-gate architecture of the FinFET, which enables the increase of the gate length and dramatically improves electrostatic performance. Beyond FinFET, the GAA (Gate All Around) device structure is one of the most promising paths for offering another disruptive leap in transistor scaling. Epitaxy is playing an increasingly critical role for enabling these device architectures, which have much more complex integration schemes and tighter process control requirements than planar devices.
 
In the past decades, germanium (Ge), silicon germanium (SiGe) and III-V semiconductor materials have garnered intense interest due to their superior electronic and optical properties and great potential to improve device performance. Silicon germanium epitaxial layers can act as a virtual substrate for growth of tensile or compressively strained layers that can serve as N and PMOS channels supporting continued scaling of Si CMOS technology. III-V materials compared to Si have about 10 times higher mobility and 2-3 times faster injection speed. CMOS devices can benefit from higher mobility and injection speed to improve operation frequency, current and power consumption, and to reduce short channel effect.
 
Strain Relaxed Silicon Germanium Buffer Layers: From Growth to Integration Challenges
A. Dube, Y. C. Huang, B. Cherian, K. Nafisi, H. Chung, and S. Chu (Applied Materials) 
Tuesday, October 4, 2016, 2:00pm
 
Group IV Epitaxy Applications for Enabling Advanced Device Scaling
B. P. Colombeau, M. Bauer, B. S. Wood, H. Chung, J. Hebb, Y. C. Huang, X. Tao, S. Chopra, A. Dube, M. Chudzik, and S. Chu (Applied Materials)
Wednesday, October 5, 2016, 2:40pm 
 
Building III-V Devices onto Large Si Wafers
X. Y. Bao, Z. Ye, D. Carlson, and E. Sanchez (Applied Materials)
Wednesday, October 5, 2016, 6:00pm
 
Optimal Target Functions for Epitaxy in New Channel Applications Such As Horizontal Gate All Around (hGAA) Device Architectures Using NanoSheets or Nanowires
M. Bauer (Applied Materials)
Friday, October 7, 2016, 8:00am
 
Growth and Etch Forms of Germanium Microcrystals on a Silicon Oxide Substrate
Y. C. Huang, M. P. Cai, H. Zhou, and H. Chung (Applied Materials)
Friday, October 7, 2016, 1:40pm
 
Applied is also hosting a reception at the event. You can register here.
 
We hope to see you there!
 
Categories: