Industry Thoughts on Full-Nodes, Inter-Nodes, Leading-Nodes and Trailing-Nodes – Part 1

Industry Thoughts on Full-Nodes, Inter-Nodes, Leading-Nodes and Trailing-Nodes – Part 1

In an environment where process nodes are no longer consistently delivering the level of improvements predicted by Moore’s Law, the industry will continue to develop “inter-nodes” as a way to deliver incremental improvements in lieu of “full-nodes.” A shift in market requirements, in part due to the rise of AI and IoT, is increasing emphasis on trailing-nodes. When it comes to leading-nodes, while EUV offers improvements in resolution, it offers only a partial solution to layer-to-layer alignment errors (i.e. overlay errors or edge placement errors – EPE). Materials engineering is needed across the spectrum of nodes, to address layer-to-layer alignment through self-aligned structures in leading-nodes, help enable inter-nodes, as well as enhance trailing-nodes.

This year’s Industry Strategy Symposium (ISS) included a very interesting panel discussion titled, "Nodes, Inter-Nodes and Real Nodes." Dan Hutcheson of VLSI Research served as the moderator and among the panelists were Mark Bohr of Intel, John Chen of NVIDIA, Peter Jenkins of ASML and Prabu Raja of Applied Materials.

Below I highlight select quotes from the panelists on each of the major topics discussed.

Inter-Nodes vs. Full-Nodes

Mark Bohr – “Full-nodes, I think at least from an Intel perspective, need to target close to a 2x transistor density improvement compared to the previous node. And full-nodes are also when we typically introduce major technology changes, such as high-K metal gate and then FinFET. Inter-nodes are really in cases where you do further optimization on that full node. You may learn something new as you’ve been through ways to improve transistor performance, or maybe some design rules to help improve density. Or maybe in some cases, they have some specialized devices like ultra-low leakage transistors or high-voltage I/O transistors. So that's what we see as the value of inter-nodes.”

In Intel’s April earnings call, the company said it has achieved 70 percent performance gains since its first 14nm products were launched through a combination of process optimizations and architectural innovation.

John Chen – “From the user perspective, there are three reasons to do the inter-node as far as I know. One is you want to improve performance…second one is…foundry changed the design rules offering higher density and cost reduction. The third one is because the next major node takes a longer time to achieve. The Moore's Law, you know, is slowing down if it has not ended.”

Trailing-Nodes vs. Leading-Nodes

Mark Bohr – “It's important to recognize that there's a growing category of products, like IoT products that don't really need, nor can they afford, a design change with billions of transistors that operate at three or four gigahertz. So there's a class of products that really can take advantage of trailing-nodes, where we can do some changes to develop the technology better-suited for those needs. I think a really good example of that is the 22FFL technology that Intel introduced last year. 22FFL takes some of the features from our older 22 nanometer technology and from our 14 nanometer technology. We combine them and enhance them to really meet the needs of IoT products…and we're looking to both modify or enhance some of the trailing-edge nodes as well as pushing the leading-edge nodes.”

Overlay Accuracy Debate: EUV and Materials Engineering

Peter Jenkins – “As I highlighted yesterday in the presentation, we give a lot more flexibility back that could be utilized potentially with EUV. Simpler processing, simpler patterning, and continue to work on the overlay challenge…”

John Chen – “Now Peter, can I ask a simple question? Teach me something: does EUV inherently have better overlay accuracy or not?”

Peter Jenkins – “Inherently? It has inherently in comparison to double or triple patterning, yes. I don’t think I can teach you anything John.”

John Chen – “Does the wavelength play such a role in terms of overlay?”

Peter Jenkins – “I wouldn’t argue fundamentally, but there are benefits from it. The reduction in patterning complexity I already mentioned. But…we’re using a vacuum system by necessity because of that wavelength. But it actually helps…in the stage…precision…and…measurement of the stage position. We actually see better overlay performance as a consequence. So there’s some practical side benefits you could say from the technology.”

Prabu Raja – “I see that [layer-to-layer vertical alignment] as the biggest roadblock in the industry. I think, John, you can talk about it more. How do we connect those billions of vias? We call it Edge Placement Error. There’s going to be limitations – at some point it’s not going to work. So that’s why I say that EUV can help to reduce the number of times to process…At some point it’s going to be fundamental. That’s why it seems more and more…the self-aligned structure, if it can align itself through the materials, is probably at some point the only solution for the alignment. So we’ve got to think more in terms of materials.”

Mark Bohr – “Feature size scaling is very important, and EUV will help us there. But alignment tolerances are not shrinking very much, so we need to develop more self-aligned techniques and process techniques to help that.”

At Applied Materials we believe there is greater opportunity for materials engineering to address challenges at “leading-nodes” (e.g. overlay, EPE) and deliver innovation at “inter-nodes” and “trailing-nodes.” We believe the rise of AI and IoT will further accelerate the opportunity for materials engineering through a renaissance of computing hardware, regardless of whether the industry believes Moore’s Law is alive within the context of classic 2D scaling.

As we’ve seen in the case of the logic transistor prior to high-K metal gate, and in NAND prior to 3D, classic Moore’s Law scaling can reach the limits of physics. While shrinking previously delivered improvements in device performance, power and area/cost (PPAC), we now need new materials and 3D techniques as well. In NAND, classic Moore’s Law (memory cells per mm2) has transitioned to 3D (memory cells per mm3). The same concept can be seen in logic (3D FinFET) and emerging memories (Intel® 3D XPoint™ technology).

The classic taxonomy of “Xnm” no longer adequately describes industry progress and value creation. It may be time to shift to a new taxonomy in which materials and 3D techniques are included in name as well as in practice. Stay tuned for more on that coming soon in part 2 of this blog.

Intel and 3D XPoint are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries.

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