Industry Leaders Examine Advancing Interconnect Scaling

May142015

Applied Materials will host a forum at the IITC* conference in Grenoble, France on May 19 to discuss ways of overcoming critical challenges in copper interconnect scaling. While much of the industry’s focus has been on transistor scaling, at the 10nm node and beyond, the interconnect is becoming a major issue. Applied Materials and guest speakers will explore the path that interconnect technology must take to keep pace with Moore’s Law in a panel titled "Advancing the Frontiers of Interconnect Scaling."

The discussion will address critical issues for the industry, including patterning extremely dense and thin copper wires and the accurate preservation of the pattern, extending dual damascene amidst the challenge of barrier scaling, and overcoming growing electro-migration and RC* delay. Concurrent with solving these issues, chipmakers must be prepared to adopt a wider range of materials and interconnect schemes for the single-digit nodes that will test the industry’s ingenuity in new ways.

To register for this event, please visit http://bit.ly/1Jh5yxj

Moderator: 

  • Mehul Naik, Ph.D., senior director, principal member of technical staff, Advanced Product Technology Development Group, Applied Materials

Panel:  

  • Daniel C. Edelstein, Ph.D. – IBM fellow and manager, BEOL Technology Strategy, IBM 
  • Christopher J. Wilson, Ph.D. – BEOL Integration team leader and technical lead, Logic Technologies Department, imec
  • Huixiong Dai, Ph.D. – distinguished member of technical staff, Advanced Product Technology Development Group, Applied Materials

Where: Maison Minatec Amphitheater, Grenoble, France

When: Tuesday, May 19, 2015

Schedule: 18:15 - 19:30 Technical Symposium

See you there!

*IITC=International Interconnect Technology Conference; RC=resistance, capacitance

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