Applied Presents Cutting-Edge Research at IEDM 2017

Applied Presents Cutting-Edge Research at IEDM 2017

At the upcoming IEEE International Electron Devices Meeting (IEDM) to be held in San Francisco from December 2-6, Applied Materials technologists will be among the world’s foremost semiconductor industry experts gathered to present on the latest research breakthroughs. Applied will showcase how solutions in our R&D pipeline can enable multiple technology inflections shaping the future.
Emerging high-performance computing, artificial intelligence (AI) and connectivity applications are driving major changes in transistor architecture, materials and process technologies. Faced with a myriad of scaling issues and performance limitations, FinFET transistor structures are expected to evolve to gate-all-around (GAA) device designs to meet ever increasing demands for more computing power. Another option for the industry is 3D sequential integration (3DSI), which supports the vertical dimension with stacked layers connected at the transistor.
Applied technologists are presenting several research papers on the various advances to expand the boundaries of new transistor technologies. We are also hosting a technical forum during IEDM. Below is the schedule of the technical sessions and events.
Technical Forum
Tuesday, Dec. 5 at 5:00 PM at the Parc 55 San Francisco Hotel, 55 Cyril Magnin St.
Applied’s technical symposium will focus on “Semiconductor Futurescapes: New Technologies, New Solutions.” IBM Research - Almaden’s vice president and lab director Dr. Jeff Welser will present developments he foresees for the next decade, including managing big data, implementing quantum and neuromorphic computing and developing viable organic microprocessors. An informal “fireside chat” will follow that explores the challenges AI poses for the semiconductor industry and its implications for society.
Short Course 1
Sunday, Dec. 3 — Boosting Performance, Ensuring Reliability, Managing Variability in Sub-5nm CMOS: Multi-Vt Engineering and Gate Performance Control for Advanced FinFET Architecture,” Applied Materials
Session 3.1 Monday, Dec. 4, 1:35 PM
(Invited) “3D Sequential Integration: Application-driven Technological Achievements and Guidelines,” CEA-Leti, MINATEC, Applied Materials, STMicroelectronics. This paper reviews potential applications ranging from computing to sensor interface, and provides an update on 3DSI device development. Low-temperature processing techniques have made great progress and high performance digital stacked FETs for computing applications can be achieved with a 500°C thermal budget.
Session 14.5 Tuesday, Dec. 5, 11:10 AM
Electron Beam Detection of Cobalt Trench Embedded Voids Enabling Improved Process Control for Middle-of-Line at the 7nm Node and Beyond,” Applied Materials. Inline detection of embedded voids in middle-of-line (MOL) cobalt metal lines is a major industry issue at 7nm and below, affecting development of new metallization solutions and monitoring during ramp and production. Applied presents a new non-destructive electron beam cobalt void detection method, leveraging an improved scanning electron microscope (SEM) imaging technique that enables an accurate detection of voids embedded inside MOL metal trenches. 
Session 22.2 Tuesday, Dec. 5, 2:30 PM
Highly Conductive Metal Gate Fill Integration Solution for Extremely Scaled RMG Stack for 5nm and Beyond,” Applied Materials. This paper describes an integrated replacement metal gate (RMG) fill solution using a cobalt reflow process combined with a thin barrier layer for future node FinFET and GAA technology.
Session 37.4, Wednesday, Dec. 6, 2:50 PM
Vertically Stacked Gate-All-Around Si Nanowire Transistors: Key Process Optimizations and Ring Oscillator Demonstration,” Imec, Applied Materials. This paper reports how oxidation-induced SiGe/Si fin deformation by STI densification is effectively suppressed by a SiN liner and that this fin protection improves controllability of nanowire formation.

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