Imagine two micrographs side-by-side, one of a transistor from an Intel 286 microprocessor from 1982 and one of a transistor from the brains of the latest smartphone. While they appear quite similar, the new one is 100 times smaller.

Panelists Witek Maszara, GlobalFoundries; Ghavam Shahidi, IBM; Thomas Skotnicki, STMicroelectronics and DK Sohn, Samsung (from left to right).

But conventional transistor scaling is reaching its limits. Beyond the 22nm technology node – sometime in the middle of this decade – traditional two-dimensional, or planar, transistors may be a thing of the past. To continue the incredible advances in speed, battery life and cost, the technology must change. Two new approaches are being considered: three-dimensional transistors and enhancements to planar transistors.

I recently attended a forum that Applied Materials hosted in San Francisco where a panel of experts debated the relative merits of these approaches. Speaking to an audience of over 200 technologists, the panel included experts from leading chip companies: GlobalFoundries, IBM, Qualcomm, Samsung and STMicroelectronics and was moderated by Professor Yuan Taur from U.C. San Diego.

The most serious shortcoming of current planar transistors is leakage current, a major source of wasted battery power. The 3D approach splits the transistor gate into multiple parts (multi-gate), allowing more effective suppression of the leakage current. 3D transistors also tend to be taller and narrower than planar ones, allowing more transistors to be packed into the same area on the chip.

Witek Maszara, principal member of technical staff at GlobalFoundries, Inc. came out in favor of 3D technology. He believes that 3D transistors offer the lowest power density, key to giving mobile devices the endurance to match their performance. Ghavam Shahidi, Fellow in the Research Division at IBM Corp., agreed that 3D transistors are promising, but will be difficult to make in high-volume manufacturing and ultimately will also suffer leakage problems, limiting their long-term viability.

Going a step further, Thomas Skotnicki, Fellow and director of Advanced Devices at STMicroelectronics asserted that 3D transistors will never be the best choice for low power applications because the structure of 3D transistors prevents the use of “body bias” which can cut leakage in half during idle periods.

Instead, Shahidi and Skotnicki favor an enhanced planar transistor approach, which aims to overcome existing scaling bottlenecks while retaining the same basic physical arrangement. In this technique, a very thin channel of “fully-depleted,” or pure, silicon is placed over a layer of insulating material – therefore called fully-depleted silicon-on-insulator (FD-SOI). By isolating the channel from the underlying silicon wafer in this way, leakage current can be greatly reduced and remarkable switching speeds achieved.

Dong Kyun Sohn, vice president in charge of the logic lab at Samsung Microelectronics’ R&D Center said that his company is still evaluating both approaches. The winner, he said, must balance design restrictions, cost, performance and scalability to achieve the best overall performance.

Offering a different perspective, Geoffrey Yeap, vice president in charge of silicon technology at Qualcomm, Inc. pointed out that every part of a smartphone, the processor, the modem, the software etc., makes different tradeoffs to add up to the best overall user experience. The key to success for a fabless company such as Qualcomm is “holistic co-design” where they engage multiple steps up and down the value chain to deliver “More than Moore” performance.

The cost of developing new technology causes chipmakers to choose the evolutionary over the revolutionary. Novel 3D technologies will require time-consuming and expensive development to bring to high-volume manufacturing. FD-SOI transistors, on the other hand, are structurally similar to today’s transistors and “only” require the refinement of existing techniques to implement. The challenges are still significant – evenly depositing a channel just a few atoms thick across a 300mm diameter wafer is not an easy task – but these are challenges the industry has historically excelled at.

Did the audience agree with the panel’s conclusions? Asked which technology would be pre-eminent in 2015, a show of hands declared FD-SOI the clear favorite, with only a few votes for 3D multi-gate. Interestingly, a significant number believes conventional planar construction can defend its incumbent position, possibly through design co-optimization and 3D chip stacking.

And beyond this decade? The experts spoke of carbon nanotubes, nanowires and quantum dots. Clearly, the pursuit of Moore’s Law may take us in some very interesting new directions – at least in theory.