Fabricating Advanced-Node, Multi-Patterning Schemes Demands Unprecedented Selectivity
Since the 1960’s, Moore's Law has described the doubling of the number of transistors in an integrated circuit approximately every two years. This amazing technological feat requires the ability to generate structures at progressively smaller scales, which has traditionally been achieved with improvements in photolithography technology.
Delays in developing commercially viable EUV lithography, however, have caused device manufacturers to shift the focus away from lithography-based scaling in favor of integration schemes that take advantage of materials properties to define tiny patterns needed to create modern electronic devices. These so-called self-aligned multi-patterning schemes require that one material be completely and cleanly removed without damaging others (Fig. 1). The ability to achieve this is referred to as extreme selectivity.
Fig. 1. The minute dimensions of multi-patterning schemes require extreme selectivity to completely remove the target material (dark blue silicon above) without damaging others (grey dielectric spacers above).
Self-aligned multi-patterning poses several issues for traditional wet etch. Wet chemistry doesn’t etch certain crystal planes of silicon, so a wet process will leave silicon residues behind, which causes defects in the pattern. Because the budget for loss of the dielectric material forming spaces in the pattern is getting much tighter, extreme selectivity is essential to prevent such loss and preserve critical dimension.
In my next post, I’ll introduce a disruptive etch technology that delivers the extreme selectivity needed for these patterning schemes as well as for further scaling of current FinFET, 3D NAND, and DRAM designs. This radically different approach will also strengthen the feasibility of fabricating gate-all-around transistors and give chip developers more freedom to create similarly innovative designs in the future.