The semiconductor industry is entering a new era of next-generation memory technologies, with several major inflections taking shape. Among these is the emergence of Magnetic RAM (MRAM). Over several posts, I’ll provide background on what is driving the adoption of MRAM, highlight some of the initial challenges and discuss progress on making STT MRAM commerically viable.
Applied has made several important developments for enabling STT MRAM manufacturing including PVD innovations on the Endura® platform and special etch technology. Using these new technologies and leveraging our Maydan Technology Center capabilities to test device arrays, we have validated the scalability and performance of SST MRAM.
Today, a typical microcontroller (MCU) is comprised of SRAM and flash as the working and storage memories respectively, in addition to logic and other specialized circuit elements. Among the issues the industry is encountering with current flash memories is minimizing the impact of the fabrication steps for the floating gate (FG) on the performance of the logic gates (Fig. 1). To achieve this, manufacturers are typically using up to 10 additional mask layers, increasing complexity and cost. Integration is even further complicated when the logic part migrates to a high-k metal gate (HKMG) scheme at the <28nm nodes, due to thermal budget limitations of HKMG.
Integrating spin-torque-transfer MRAM (STT MRAM) in the back-end of line (BEOL) on the other hand is easier with only three additional masks (Fig. 1). Further, energy consumption for flash is large compared to STT MRAM. These promising characteristics of STT MRAM: fast speed, non-volatility, low power and easy BEOL integration at low temperatures is the reason most major logic and memory fabs are developing STT MRAM technology. In addition to MCUs, STT MRAM is also being developed for replacing SRAM as last-level cache memory for <10nm nodes, due to higher densities achievable for STT MRAM compared to SRAM.
Each unit cell of STT MRAM consists of magnetic tunnel junctions (MTJ), which in the most basic form are composed of a thin dielectric tunneling barrier film (~10Å thick MgO) sandwiched between two ferromagnetic films (~10-30Å thick CoFeB). Practical MTJs feature many additional thin film layers in the MTJ stack (see Fig. 2a for example) and have been manufactured as read sensors in hard disk drives (HDDs) since 2007.
However, the requirements are quite different for isolated MTJ devices in HDDs versus arrays of perpendicular MTJ (pMTJ) devices in STT MRAM. Innovations in pMTJ film stack deposition and etch process equipment are critical for manufacturing STT MRAM at competitive density/performance. In addition, the wafer starts in memory fabs where STT MRAM would be manufactured are 10-20X higher than a HDD head fab, so the equipment up time is a key factor to be considered during design.
Applied Materials has developed a multi-cathode PVD chamber as well as various in-situ thermal treatment chambers on the company’s Endura platform for pMTJ stack deposition (multi-layers of sub-Å precision with controlled microstructure and clean interfaces). In addition, special etch technology for non-volatile magnetic materials in dense arrays was developed to etch pMTJ arrays.
To evaluate the performance of the pMTJ deposition and etch equipment, 1R pMTJ array test chips were designed and fabricated at our Maydan Technology Center. The smallest cell size of 130nmx130nm (Fig. 2) is equivalent to 22F2 at the 28nm node and equivalent to ~ 1Gb density. These test chips were electrically characterized at Qualcomm and the results jointly presented at IEDM 2015 and IEDM 2016.[2, 3] These results, discussed in the following paragraphs, highlight the performance of pMTJ arrays fabricated using the Endura PVD system and special etch technology.
One key performance metric is TMR% (tunnel magnetoresistance) of etched MTJ arrays. Average TMR ~150% was obtained for pMTJ arrays with a 130nm pitch and 50nm diameter (Fig. 3). The sigma/mean for the resistance (RP) was <8%. Both these values indicates low etch damage during etching. By optimizing the free layer (FL) material in the pMTJ stack, low P-AP switching current of ~90uA (35ns pulse switching) was obtained for the arrays (Fig. 4).
Finally, by optimizing the MgO deposition chamber hardware design, the breakdown voltage of the ~10Å MgO tunneling barrier layer was significantly improved from ~ 1.2V (standard) to ~ 1.5V (improved) as shown in Fig. 5. This is critical for improving the endurance to >1015write cycles as demonstrated in our work.I will discuss this further in my next blog.
Lin et al., IEEE Trans of Magnetics, vol. 51 2015 p4401503
Proliferating mobile, “smart” electronic consumer products, Internet of Things devices, and high-performance computing applications are driving greater complexity in wafer-level packaging schemes and expanding the number of electrochemical deposition steps in their fabrication.