Contact Resistance and its Role in Limiting Transistor Performance
In logic devices, contacts and local interconnects (the first level of metal wires shown in Fig. 1) form the critical electrical pathways between the transistors and the rest of the circuit. Low resistivity is therefore crucial for robust and reliable device performance. Consequently, low-resistivity CVD tungsten (W) has historically been used for logic contact and local interconnect fill.
As devices have scaled downward, numerous innovations have enhanced transistor performance, but the accompanying scaling of interconnect dimensions has reached the point at which contact resistance is becoming an obstacle to realizing optimum transistor performance. This is because as the cross-section of the interconnect decreases, a growing proportion of the volume is occupied by metal liner, barrier and nucleation layers, leaving less volume for the conducting W fill.
To date, high-resistivity TiN has been predominantly used as an adhesion layer for CVD W and to block fluorine penetration during the bulk fill process. W does not grow directly on TiN; thus, it requires deposition of a nucleation layer before the fill step. As logic devices scale through the 10nm node and beyond, the maximum critical dimension of the local interconnect will be <25nm. This leaves <12nm for low-resistance W fill, which results in high overall contact resistance (Fig. 2). In addition, the interfaces between each of the layers add to the overall resistance of the contact.
In my next blog post, I’ll explain how materials engineering is reducing contact resistance, making it possible to extend tungsten technology to next-generation devices.
Visit the Applied Materials web site to learn more about this technology.