Applied Materials is chairing a panel discussion with memory technology leaders including Intel, Samsung, SK hynix and Western Digital to address new types of storage class memory as part of the eighth IEEE International Memory Workshop on May 16.
One of the biggest developments taking place in the semiconductor industry is the emergence of 3D NAND memory technology. Products are available today that feature 3D NAND devices. It has taken years to become a reality — since Toshiba first discussed the concept of 3D NAND at the VLSI Symposium in 2007 – and now it is poised to replace planar NAND flash memory for storage.
The path that has led to this point is similar to what happened with the logic roadmap; despite innovative workarounds, the era of traditional planar "shrinks" for NAND is running out of steam. And, just as with logic, it has required significant technical advances to overcome the formidable challenges to successfully manufacture complex vertical 3D NAND designs.
The past several weeks have been big for 3D NAND flash technology.Samsung announced it had begun mass production of its first 3D vertical NAND flash memory, a 128GB chip using 24 cell layers. Following this news, at the Flash Memory Summit, Samsung Executive Vice President and General Manager E.S. Jung delivered a special keynote address, titled ”Ushering in the 3D Memory Era with Vertical NAND.” In his talk, he told the audience that Samsung’s implementation of 3D NAND was delivering impressive performance benefits over its previous 19nm planar NAND: 2 times higher density, 2 times faster write speed, 50 percent less power consumption and 10 times better endurance.
This week I’ll be participating in a panel discussion at the Flash Memory Summit in Santa Clara, CA. The panel’s topic, Flash Below 20nm: What is Coming and When?, couldn’t be more timely. Particularly in light of a leading NAND manufacturer’s recent announcement that they will begin mass production of the semiconductor industry’s first 3D vertical NAND flash memory later this year.3D NAND presents some significant changes to the traditional semiconductor manufacturing model.
With the 5th Annual International Memory Workshop (IMW) coming up next week in Monterey, CA I wanted to point out a recent article from Semiconductor Manufacturing & Design. As the cell-to-cell interference issues characteristic of sub-20nm manufacturing processes threaten to keep NAND from moving to smaller nodes, the major players in the NAND flash market are looking at different approaches to implementing NAND in a 3D chip architecture. The article provides a great summary of the different approaches to 3D NAND customers are adopting and when to expect those technologies to hit the market.
Below is a short excerpt of an article I submitted to IEEE Spectrum that looks at the emerging memory technologies being considered to help smartphones and tablets meet the demand for more energy efficient data storage. To access the complete article, visit the IEEE Spectrum web site."Our smartphones and ultrathin laptops rely on a triumvirate of memory technologies—SRAM, DRAM, and flash—each customized for a specific purpose. They’ve all been fabulous workhorses, but now these memories are struggling to keep up with the steady demand for chips that are faster, cheaper, more reliable, and more energy efficient.