transistors

Applied Presents Cutting-Edge Research at IEDM 2017

Applied Presents Cutting-Edge Research at IEDM 2017

At the upcoming IEEE International Electron Devices Meeting (IEDM) to be held in San Francisco from December 2-6, Applied Materials technologists will be among the world’s foremost semiconductor industry experts gathered to present on the latest research breakthroughs. Applied will showcase how solutions in our R&D pipeline can enable multiple technology inflections shaping the future.
The Shift to Materials-Enabled 3D

The Shift to Materials-Enabled 3D

Every year, media outlets publish year-end reviews and outlooks for the New Year. Solid State Technology, a leading magazine providing the latest electronics manufacturing news, analysis and product information related to semiconductor manufacturing features an annual outlook and invited Randhir Thakur, Executive Vice President, General Manager, Silicon Systems Group, Applied Materials to give his assessment of the major trends for 2014. He identified the shifts to 20 nanometer designs, FinFET transistors and 3D NAND as the game-changing innovations and discussed how Applied is focused on providing the precision materials engineering solutions to address the challenges involved in advancing these technologies.
Happy 66th, Transistor!

Happy 66th, Transistor!

Today marks the 66th birthday of the first working transistor; an opportune time to look back at how far this technological marvel has come. With 66 years of innovations behind it, today’s transistor looks quite different from when it first hit the scene.First, there are so many of them around today. It’s estimated that more than 1200 quintillion transistors will be manufactured in 2015, making the transistor the most ubiquitous man-made device on the planet.
Mike Splinter Awarded Semiconductor Industry’s Highest Honor

Mike Splinter Awarded Semiconductor Industry’s Highest Honor

Applied Materials Executive Chairman Mike Splinter was recognized this week at the Semiconductor Industry Association’s (SIA) 36th annual awards dinner, where he received the Robert N. Noyce Award, the industry’s highest honor, for his significant contributions to the U.S. semiconductor industry in technology and public policy.A well-known and respected industry veteran, Mike successfully led Applied Materials as CEO for more than a decade, expanding the company’s position as a leading global equipment provider to the semiconductor, display and solar industries, and helping to drive critical innovations in transistor design to further Moore’s Law, the foundation of all modern day electronics.
Applied Materials’ Mike Splinter Discusses Latest Mobility Trends on FOX Business

Applied Materials’ Mike Splinter Discusses Latest Mobility Trends on FOX Business

Applied Materials Executive Chairman Mike Splinter was interviewed by Liz Claman earlier this week as part of FOX Business’ “Three Days in the Valley” series. Mike explained how materials innovations are key to enabling the low power, high performance chips used in cutting-edge mobile products such as wearables and smartphones like those launched recently by Samsung and Apple.
2013 Applied Materials Analyst Meeting & SEMICON West Activities

2013 Applied Materials Analyst Meeting & SEMICON West Activities

Cutting-edge technology advancements in the semiconductor and display equipment manufacturing industries increasingly are being driven by mobility. The rapid growth in smartphones and tablets has propelled manufacturers to explore new advanced materials, manufacturing processes, and transistor technologies in order to keep up with the accelerating pace of innovation.    Mobility applications demand higher resolution and higher performance in LCD, OLED and touch panel displays.  Enhanced viewing experiences through OLED and flexible displays, combined with thinner, lighter, greener and more portable form factors, are right around the corner. On July 8 beginning at 1:00pm PT at our Santa Clara, Calif. headquarters, Applied Materials will discuss these trends and the company’s role in advancing the semiconductor and display industries during our annual Analyst Meeting.
Overcoming Shallow Trench Isolation Challenges for Sub-20 Nanometer

Overcoming Shallow Trench Isolation Challenges for Sub-20 Nanometer

To prevent electrical current leaking between adjacent transistors, state-of-the-art microchips feature shallow trench isolation (STI) to isolate transistors from each other. Key steps in the STI process involve etching a pattern of trenches in the silicon, depositing dielectric materials to fill the trenches, and removing the excess dielectric using technologies such as chemical-mechanical planarization (CMP). But as the industry scales to sub-20 nanometers significant challenges for the STI etch step are emerging.