Applied Materials’ Endura Ventura PVD, the first metallization solution for high-volume manufacturing of high aspect ratio through-silicon via structures enables the smaller, lower power, high-performance integrated 3D chips required for high-end electronic devices.
This TEM image taken at Applied Materials’ Maydan Technology Center shows a series of 20nm-wide trenches in cross section. These tiny structures – about 1/5000th of the diameter of an average human hair – are similar to the interconnects used to wire the billions of transistors in next-generation microchips. You can see that each trench is partially filled with copper, all the way to the bottom, with no gaps or voids. This was achieved using Applied’s revolutionary copper reflow technology. For a primer on how interconnects are made and how copper reflow works, see this video.
Why is a smartphone like a hummingbird? Neither can go more than a few hours without refueling, or bad things happen. (If you answered that smartphone owners are often forced to flutter around looking for a power outlet, I’ll accept that, too.)
Do you know where the power goes? As the graphic shows, around half your battery is spent on the display alone. And of that, the vast majority is used simply to power the backlight that all LCDs need. (The situation for AMOLED displays is similar, but for different reasons. That’s a subject for a future blog.)
Clearly, improving the power efficiency of the display is a powerful way to improve...
Given that today’s advanced chips can contain billions of transistors, 60 miles of copper wiring and 10 billion vertical connections between metal layers, the challenges and potential pitfalls this level of complexity presents are mind-boggling. One major problem on the horizon at 20nm and below is the threat of voids forming in the vertical interconnects commonly called vias.