With the 5th Annual International Memory Workshop (IMW) coming up next week in Monterey, CA I wanted to point out a recent article from Semiconductor Manufacturing & Design. As the cell-to-cell interference issues characteristic of sub-20nm manufacturing processes threaten to keep NAND from moving to smaller nodes, the major players in the NAND flash market are looking at different approaches to implementing NAND in a 3D chip architecture. The article provides a great summary of the different approaches to 3D NAND customers are adopting and when to expect those technologies to hit the market.
Mobile computing is now everywhere, more than ever before as a result of faster and more capable smart phones, tablets, and laptops.
Universal mobility and instant-on connectivity may herald a new era in computing, but improvements in key technologies are necessary if we are going to keep up with consumers’ constant demand for higher performance, longer battery life and ultra-sleek profiles.
To address these technology improvements and answer key questions that may significantly impact the way we interface with an increasingly connected world, Applied Ventures and the MIT Club of Northern California (MITCNC) will host a lively panel discussion with innovators from across the memory value chain on Wednesday, February 1 at 6:30pm in Santa Clara, Calif.
[edit: you can read a report from the session here.]
Every two years, your hard-earned dollar buys twice as much memory capacity. This “law” has held true for decades, and shows no sign of slowing. Sixty years ago, a state-of-the-art memory device was a tube full of mercury, with 500 bits of data stored as acoustic waves travelling up and down between transducers at either end. Today, Flash memory cards containing more than a hundred billion bits can be found at the supermarket, next to the chewing gum.
This relentless progress is the result of the hard work of thousands of researchers and engineers around the globe who are dedicated to advancing memory technology. A few hundred of those technologists (and this humble blogger) met earlier this week at the 2011 IEEE International Memory Workshop in Monterey, California to discuss the future of memory technology.
Semiconductor Manufacturing & Design’s David Lammers recently covered Applied Materials’ analyst meeting and published an article on the growth and wider adoption of solid-state drives as well as what is driving wafer-level packaging and through-silicon vias.