With the 5th Annual International Memory Workshop (IMW) coming up next week in Monterey, CA I wanted to point out a recent article from Semiconductor Manufacturing & Design. As the cell-to-cell interference issues characteristic of sub-20nm manufacturing processes threaten to keep NAND from moving to smaller nodes, the major players in the NAND flash market are looking at different approaches to implementing NAND in a 3D chip architecture. The article provides a great summary of the different approaches to 3D NAND customers are adopting and when to expect those technologies to hit the market.
Below is a short excerpt of an article I submitted to IEEE Spectrum that looks at the emerging memory technologies being considered to help smartphones and tablets meet the demand for more energy efficient data storage. To access the complete article, visit the IEEE Spectrum web site.
"Our smartphones and ultrathin laptops rely on a triumvirate of memory technologies—SRAM, DRAM, and flash—each customized for a specific purpose. They’ve all been fabulous workhorses, but now these memories are struggling to keep up with the steady demand for chips that are faster, cheaper, more reliable, and more energy efficient.
Every two years, your hard-earned dollar buys twice as much memory capacity. This “law” has held true for decades, and shows no sign of slowing. Sixty years ago, a state-of-the-art memory device was a tube full of mercury, with 500 bits of data stored as acoustic waves travelling up and down between transducers at either end. Today, Flash memory cards containing more than a hundred billion bits can be found at the supermarket, next to the chewing gum.
This relentless progress is the result of the hard work of thousands of researchers and engineers around the globe who are dedicated to advancing memory technology. A few hundred of those technologists (and this humble blogger) met earlier this week at the 2011 IEEE International Memory Workshop in Monterey, California to discuss the future of memory technology.