Applied's Sree Kesapragada and Miller Allen, discuss the Endura Cirrus HTX which meets chipmakers’ copper interconnect patterning needs by extending the TiN metal hardmask —the industry’s material of choice — to the 10nm and below nodes.
Applied Materials’ Endura Ventura PVD, the first metallization solution for high-volume manufacturing of high aspect ratio through-silicon via structures enables the smaller, lower power, high-performance integrated 3D chips required for high-end electronic devices.
The Endura® system is recognized as the most successful metallization tool in the history of the semiconductor industry. Since its introduction, through continuous infusions of new innovations and process technologies, it has enabled customers to advance Moore’s Law from the .75 micron node to today’s sub-20 nanometer nodes, and can continue beyond to sub-10 nanometer designs.
To appreciate what made the Endura a truly landmark system, and how the value it provides has been sustained over decades, I'd like to reference the recent VLSIresearch feature and highlight some key points.
This TEM image taken at Applied Materials’ Maydan Technology Center shows a series of 20nm-wide trenches in cross section. These tiny structures – about 1/5000th of the diameter of an average human hair – are similar to the interconnects used to wire the billions of transistors in next-generation microchips. You can see that each trench is partially filled with copper, all the way to the bottom, with no gaps or voids. This was achieved using Applied’s revolutionary copper reflow technology. For a primer on how interconnects are made and how copper reflow works, see this video.
Given that today’s advanced chips can contain billions of transistors, 60 miles of copper wiring and 10 billion vertical connections between metal layers, the challenges and potential pitfalls this level of complexity presents are mind-boggling. One major problem on the horizon at 20nm and below is the threat of voids forming in the vertical interconnects commonly called vias.
In part one, Russ Perry, dielectric guru, talked about the evolution of dielectric films – the insulation that cradles the 50 plus miles of copper wiring in a modern microprocessor.
Now, Applied’s researchers have gone a step further. They’ve developed a new technology that reinforces the dielectric at the atomic level, making it more power-efficient and mechanically stronger.
With the aid of various plastic and silicon props, Russ explains how Applied’s new Onyx technology works. This breakthrough will enable chipmakers to fabricate the industry’s lowest capacitance interconnects while making the whole structure tough enough to withstand the...
When it comes to microchip technology, transistors seem to get all the attention. But did you know that the transistor layer only makes up 10% of a modern logic chip?
The other 90% is made up of interconnect layers – the three-dimensional maze of copper wires that make connections between all those transistors and the outside world. From a volume perspective, that makes the dielectric insulator that supports all that copper the most important material in all of chipmaking!
According to Stork, though significant challenges remain with vertical interconnects using through-silicon vias (TSVs), the semiconductor industry is on the verge of turning this into a manufacturing technology.